std_logic_vector representing one bit

A

ALuPin

Hi,

I have the following problem, maybe I am to blind to see
the solution :eek:)


signal declaration:

signal li3_q : std_logic_vector(0 downto 0);

The signal was created that way when instantiating a RAM component.

How can I do an if-then-else?


if li3_q='1' then
...
else
....
end if;

The compiler (Altera QuartusII) says:
"Error: VHDL error at ... : can't determine definition of operator "="
-- found 0 possible definitions"

Would be thankful for any explanation.

Kind regards

Andrés V.
 
V

valentin tihomirov

Vector is not the same as a signal. Try if VEC = "1" then or VEC = (others
=> '1').
 
E

Egbert Molenkamp

It is a vector .. so you should treat it as a vector : if li3_q="1"
or if li3_q(0)='1'

Egbert Molenkamp
 
E

Egbert Molenkamp

valentin tihomirov said:
Vector is not the same as a signal. Try if VEC = "1" then or VEC = (others
=> '1').
if VEC = (others => '1') then ..

is not correct. Correct is:

if VEC=(VEC'RANGE=>'1') then
(but I'm not sure if MaxPlus supports this).

Egbert Molenkamp
 

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