std_logic_vector representing one bit

Discussion in 'VHDL' started by ALuPin, Feb 25, 2004.

  1. ALuPin

    ALuPin Guest

    Hi,

    I have the following problem, maybe I am to blind to see
    the solution :eek:)


    signal declaration:

    signal li3_q : std_logic_vector(0 downto 0);

    The signal was created that way when instantiating a RAM component.

    How can I do an if-then-else?


    if li3_q='1' then
    ...
    else
    ....
    end if;

    The compiler (Altera QuartusII) says:
    "Error: VHDL error at ... : can't determine definition of operator "="
    -- found 0 possible definitions"

    Would be thankful for any explanation.

    Kind regards

    Andrés V.
     
    ALuPin, Feb 25, 2004
    #1
    1. Advertising

  2. Vector is not the same as a signal. Try if VEC = "1" then or VEC = (others
    => '1').
     
    valentin tihomirov, Feb 25, 2004
    #2
    1. Advertising

  3. It is a vector .. so you should treat it as a vector : if li3_q="1"
    or if li3_q(0)='1'

    Egbert Molenkamp


    "ALuPin" <> wrote in message
    news:...
    > Hi,
    >
    > I have the following problem, maybe I am to blind to see
    > the solution :eek:)
    >
    >
    > signal declaration:
    >
    > signal li3_q : std_logic_vector(0 downto 0);
    >
    > The signal was created that way when instantiating a RAM component.
    >
    > How can I do an if-then-else?
    >
    >
    > if li3_q='1' then
    > ...
    > else
    > ....
    > end if;
    >
    > The compiler (Altera QuartusII) says:
    > "Error: VHDL error at ... : can't determine definition of operator "="
    > -- found 0 possible definitions"
    >
    > Would be thankful for any explanation.
    >
    > Kind regards
    >
    > Andrés V.
     
    Egbert Molenkamp, Feb 25, 2004
    #3
  4. "valentin tihomirov" <> schreef in
    bericht news:c1i8mg$1jaanc$-berlin.de...
    > Vector is not the same as a signal. Try if VEC = "1" then or VEC = (others
    > => '1').
    >

    if VEC = (others => '1') then ..

    is not correct. Correct is:

    if VEC=(VEC'RANGE=>'1') then
    (but I'm not sure if MaxPlus supports this).

    Egbert Molenkamp
     
    Egbert Molenkamp, Feb 25, 2004
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Replies:
    3
    Views:
    1,855
    Timothy Bendfelt
    Jan 19, 2007
  2. Replies:
    9
    Views:
    1,049
    Juha Nieminen
    Aug 22, 2007
  3. Thomas Rouam
    Replies:
    6
    Views:
    1,190
  4. Tobias Baumann
    Replies:
    14
    Views:
    1,348
    Tobias Baumann
    Feb 21, 2012
  5. Jeff.M
    Replies:
    6
    Views:
    204
    Lasse Reichstein Nielsen
    May 4, 2009
Loading...

Share This Page