std_logic_vector to string in hex format

Discussion in 'VHDL' started by Mad I.D., Aug 29, 2009.

  1. Mad I.D.

    Mad I.D. Guest

    Hello. I have a
    std_logic_vector let's say X"ABCD".

    And i have

    variable temp : string (4 downto 1);

    How do I put ABCD in variable temp?

    Thank you. I'm trying with the 'image but it only works on scalars.
     
    Mad I.D., Aug 29, 2009
    #1
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  2. Mad I.D.

    Mad I.D. Guest

    On Aug 29, 6:45 pm, Jonathan Bromley <>
    wrote:
    /cut

    Jonathan, thank you very much. this was helpful !
     
    Mad I.D., Aug 29, 2009
    #2
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  3. Mad I.D.

    Mad I.D. Guest

    On Aug 29, 6:45 pm, Jonathan Bromley <>
    wrote:
    /cut

    Sorry Jonathan but I must ask something about the code.
    My VHDL knowledge is not perfect so I don't undestand this :

    I see that you had to create a new subtype so the compiler wouldn't
    report that selector is unconstrained.

    Can you explain this:
    slv4'(s_norm(i*4 to i*4+3))

    I never saw this kind of value assignment using ' (for attributes) and
    don't know what to ask google. Please if you could provide a useful
    link or just explain :) I would like to learn.

    Thank you again !
    Sorry for my eng.
     
    Mad I.D., Aug 29, 2009
    #3
  4. Mad I.D.

    Mad I.D. Guest

    On Aug 29, 8:09 pm, "Mad I.D." <> wrote:
    > On Aug 29, 6:45 pm, Jonathan Bromley <>
    > wrote:
    > /cut
    >
    > Sorry Jonathan but I must ask something about the code.
    > My VHDL knowledge is not perfect so I don't undestand this :
    >
    > I see that you had to create a new subtype so the compiler wouldn't
    > report that selector is unconstrained.
    >
    > Can you explain this:
    > slv4'(s_norm(i*4 to i*4+3))
    >
    > I never saw this kind of value assignment using ' (for attributes) and
    > don't know what to ask google. Please if you could provide a useful
    > link or just explain :) I would like to learn.
    >
    > Thank you again !
    > Sorry for my eng.


    OK, I found it :)
    "Qualified expressions"
     
    Mad I.D., Aug 29, 2009
    #4
  5. Mad I.D.

    KJ Guest

    On Aug 29, 2:09 pm, "Mad I.D." <> wrote:

    >
    > Can you explain this:
    > slv4'(s_norm(i*4 to i*4+3))
    >
    > I never saw this kind of value assignment using ' (for attributes) and
    > don't know what to ask google. Please if you could provide a useful
    > link or just explain :) I would like to learn.


    In this case, the ' does not indicate an attribute, instead it is used
    to state that the thing to the right of the ' (in this case "(s_norm
    (i*4 to i*4+3))") is of the type specified by what is to the left of
    the ' (in this case "slv4"). The reason you need to tell it this is
    because the data type of "(s_norm(i*4 to i*4+3))" is ambiguous. In
    this situation the ' is called a 'type qualifier'.

    A simpler example of the need for a type qualifier is something like
    "0101". Should this be interpreted as a std_logic_vector, a
    bit_vector, a string? Without any context, it is impossible to tell.
    In many situations, the compiler can figure it out based on what
    "0101" is being assigned to, in other cases it can't. In those
    situations where the compiler complains about the type being
    ambiguous, you have to explicitly tell it what the type is so if
    "0101" is meant to be treated as a string then you would say

    string'("0101")

    As an aside, you'll probably find the conversion of data types to
    strings will find many uses, in testbenches as well as design code. I
    would suggest that you first create a function along the lines of what
    Jonathon suggested but instead of working with std_logic_vector, have
    it work with an input string. I'd also get rid of the limitation that
    requires the input string to have only a multiple of 4 (don't assert
    with a failure, just pad the left with the appropriate number of
    zeros). So your basic function with all the gory code fits the
    following form

    function HexImage(L: string) return string;

    Now you can build on this by creating heximage functions that work
    with all the vector types quite easily, without having to rewrite
    anything, instead you'll be building on this one basic function (see
    code below).

    Those functions presuppose that there is a function called 'image'
    that can translate a particular data type (for example
    'std_logic_vector') into a string of ones and zeros. You'll have to
    write those functions too, but they are pretty simple (see example
    below for 'bit' and 'bit_vector').

    By building up a set of functions in this way you can pretty quickly
    get yourself a full library of functions that convert from all of the
    basic data types (including vectors) into strings. The most effective
    way to do this is to have your base function (the one that has the
    nitty, gritty code with the case, if, etc.) work with strings rather
    than std_logic_vector.

    In fact, you can see the value of using strings as function I/O right
    in the use of the other conversion functions themselves that I've
    shown because to build up the bigger functions, I rely on using other
    lower level functions. By normalizing on strings for function I/O for
    the lowest level conversion function, it simplifies things quite a
    bit.

    Kevin Jennings

    -- Start of heximage functions
    function HexImage(L: bit_vector) return String is
    begin
    return(HexImage(image(L)));
    end function HexImage;

    function HexImage(L: std_ulogic_vector) return String is
    begin
    return(HexImage(image(to_x01(L))));
    end function HexImage;

    function HexImage(L: std_logic_vector) return String is
    begin
    return(HexImage(image(to_x01(L))));
    end function HexImage;

    function HexImage(L: signed) return String is
    begin
    return(HexImage(image(L)));
    end function HexImage;

    function HexImage(L: unsigned) return String is
    begin
    return(HexImage(image(L)));
    end function HexImage;
    -- End of heximage functions
    -- Start of an example image function
    function image(L: bit) return String is
    constant bit_image: String := bit'image(L);
    begin
    return(bit_image(2 to 2));
    end function image;

    function image(L: bit_vector) return String is
    variable Lx: bit_vector(1 to L'length);
    variable RetVal: String(1 to L'length);
    begin
    Lx := L;
    for i in Lx'range loop
    RetVal(i to i) := image(Lx(i));
    end loop;
    return(RetVal);
    end function image;
    -- End of an example image function
    Kevin Jennings
     
    KJ, Aug 29, 2009
    #5
  6. Mad I.D.

    KJ Guest

    On Aug 29, 4:17 pm, Jonathan Bromley <>
    wrote:
    > On Sat, 29 Aug 2009 13:05:10 -0700 (PDT), KJ...
    >
    > >would suggest that you first create a function along the lines of what
    > >Jonathon suggested but instead of working with std_logic_vector, have
    > >it work with an input string.  I'd also get rid of the limitation that
    > >requires the input string to have only a multiple of 4 (don't assert
    > >with a failure, just pad the left with the appropriate number of
    > >zeros).

    >
    > All very sensible.  Your stringification of assorted
    > vector types before generating other representations
    > is an interesting idea, though I'm not 100% sure I
    > really like it - it seems a pity to lose information
    > about the source data object's type so early in the
    > conversion process.
    >


    Then maybe think of it as converting the source data type into the
    target data type early in the conversion process instead.

    As a general rule, we're likely in agreement that the conversion to
    some generic type like 'string' in order to reuse something is not
    always good practice since this can also be abused to defeat the type
    checking that is a very useful part of the language. I'm guessing
    this is the reason for your less than '100% sure'. However, in this
    case I don't think there is any abuse of type checking since there is
    still a gatekeeper with the various 'image' functions each of which
    works only with one specific data type and will always return a
    properly formatted string. Any required checking should be done
    there.

    > In self-defence I should point out that I was doing
    > my best to illustrate, in one small example, a bunch
    > of tricks that are generally useful in such applications:
    > normalization of vector ranges, unconstrained parameters
    > and return types, type qualification, and the use of
    > assertions to catch undesirable/unexpected conditions.


    My agenda was to show examples of code reuse, broadening a specific
    problem into a more general problem/solution and then demonstrating
    how that can sometimes results in being able to quickly and easily
    build on the general solution to provide not only the specific
    solution, but other examples of other specific solutions.

    > I hope it didn't throw the OP too much off the scent.


    That's why we post though, isn't it? To give the posters and others
    other scents to sniff at.

    Kevin Jennings
     
    KJ, Aug 29, 2009
    #6
  7. Mad I.D.

    JimLewis Guest

    On Aug 29, 7:16 pm, David Bishop <> wrote:
    > Mad I.D. wrote:
    > > Hello. I have a
    > > std_logic_vector let's say X"ABCD".

    >
    > > And i have

    >
    > > variable temp : string (4 downto 1);

    >
    > > How do I put ABCD in variable temp?

    >
    > Get the following package:http://www.eda.org/fphdl/std_logic_1164_additions.vhdl
    > (original page:http://www.eda.org/fphdl)
    >
    > Load this page, then:
    >
    > temp := to_hstring (slv_var);


    In the newer version of ModelSim if you turn on the VHDL-2008
    switch this works without adding the package.

    For Aldec, they have already compiled this package for
    you in the library ieee_proposed. I suspect if you turn
    on the VHDL-2008 flag that it will also work without referencing
    the package.

    Best,
    Jim
     
    JimLewis, Sep 16, 2009
    #7
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