STD_LOGIC_VECTOR vs. UNSIGNED vs. SIGNED

Discussion in 'VHDL' started by Jeremy Pyle, Jun 27, 2003.

  1. Jeremy Pyle

    Jeremy Pyle Guest

    Ok, got a question about the three types: STD_LOGIC_VECTOR, UNSIGNED and
    SIGNED. The difference between UNSIGNED and SIGNED is pretty
    obvious......SIGNED will always give a result in 2's compliment where
    UNSIGNED will never give a result in 2's compliment. What about
    STD_LOGIC_VECTOR, do I have to worry if I pass in something like this:

    process
    variable i : integer range 0 to 511 := 511;
    variable j : STD_LOGIC_VECTOR(8 downto 0);
    begin
    j := CONV_STD_LOGIC_VECTOR(i, 9);

    will this produce the vector as expected of 111111111 or will it sometimes
    produce a 2's compliment vector? Can I get unexpected results doing
    something like this?

    Thanks,

    Jeremy
     
    Jeremy Pyle, Jun 27, 2003
    #1
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  2. You can find more on this subject in the FAQ
    http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#4.11

    You are very clear in your question, indeed SIGNED and UNSIGNED
    are pretty obvious. But the interpretation of STD_LOGIC_VECTOR?
    It depends if you are synopsys' package STD_LOGIC_UNSIGNED it will
    have an unsigned interpretation, and with synopsys' package
    STD_LOGIC_SIGNED it will be signed.

    Egbert Molenkamp

    "Jeremy Pyle" <> wrote in message
    news:xSMKa.34025$...
    > Ok, got a question about the three types: STD_LOGIC_VECTOR, UNSIGNED and
    > SIGNED. The difference between UNSIGNED and SIGNED is pretty
    > obvious......SIGNED will always give a result in 2's compliment where
    > UNSIGNED will never give a result in 2's compliment. What about
    > STD_LOGIC_VECTOR, do I have to worry if I pass in something like this:
    >
    > process
    > variable i : integer range 0 to 511 := 511;
    > variable j : STD_LOGIC_VECTOR(8 downto 0);
    > begin
    > j := CONV_STD_LOGIC_VECTOR(i, 9);
    >
    > will this produce the vector as expected of 111111111 or will it sometimes
    > produce a 2's compliment vector? Can I get unexpected results doing
    > something like this?
    >
    > Thanks,
    >
    > Jeremy
    >
    >
     
    Egbert Molenkamp, Jun 27, 2003
    #2
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  3. Jeremy Pyle

    Niv Guest

    You should really be using the IEEE numeric.std package now & not the
    synopsys signed & unsigned ones. It does become clear after a while,
    promise.

    Niv.

    "Egbert Molenkamp" <> wrote in message
    news:bdgsb0$rm6$...
    > You can find more on this subject in the FAQ
    > http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#4.11
    >
    > You are very clear in your question, indeed SIGNED and UNSIGNED
    > are pretty obvious. But the interpretation of STD_LOGIC_VECTOR?
    > It depends if you are synopsys' package STD_LOGIC_UNSIGNED it will
    > have an unsigned interpretation, and with synopsys' package
    > STD_LOGIC_SIGNED it will be signed.
    >
    > Egbert Molenkamp
    >
    > "Jeremy Pyle" <> wrote in message
    > news:xSMKa.34025$...
    > > Ok, got a question about the three types: STD_LOGIC_VECTOR, UNSIGNED and
    > > SIGNED. The difference between UNSIGNED and SIGNED is pretty
    > > obvious......SIGNED will always give a result in 2's compliment where
    > > UNSIGNED will never give a result in 2's compliment. What about
    > > STD_LOGIC_VECTOR, do I have to worry if I pass in something like this:
    > >
    > > process
    > > variable i : integer range 0 to 511 := 511;
    > > variable j : STD_LOGIC_VECTOR(8 downto 0);
    > > begin
    > > j := CONV_STD_LOGIC_VECTOR(i, 9);
    > >
    > > will this produce the vector as expected of 111111111 or will it

    sometimes
    > > produce a 2's compliment vector? Can I get unexpected results doing
    > > something like this?
    > >
    > > Thanks,
    > >
    > > Jeremy
    > >
    > >

    >
    >
     
    Niv, Jun 28, 2003
    #3
  4. Jeremy Pyle wrote:

    > will this produce the vector as expected of 111111111 or will it sometimes
    > produce a 2's compliment vector? Can I get unexpected results doing
    > something like this?



    Here's an example using numeric_std.

    -- Mike Treseler

    ------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity qual is
    end qual;

    architecture sim of qual is
    begin
    what : process is
    constant a : signed := "111"; -- -1
    constant b : unsigned := "111"; -- 7
    constant c : string := "111"; -- "111"
    constant d : std_logic_vector := "111";

    begin
    report "a = " & integer'image( to_integer(a));
    report "a > 2 is " & boolean'image( a>2 );
    report "b = " & integer'image( to_integer(b));
    report "b > 2 is " & boolean'image( b>2 );
    report "c = """ &c & """ ";
    report "c > ""2"" is " & boolean'image( c>"2" );
    report "c > ""1"" is " & boolean'image( c>"1" );
    report "d = ""111"" ";
    report "d > ""010"" is " & boolean'image( d>"001");
    wait;
    end process what;
    end sim;

    --VSIM 4> vsim -c qual; run

    --# Loading work.qual(sim)
    --# ** Note: a = -1
    --# ** Note: a > 2 is false
    --# ** Note: b = 7
    --# ** Note: b > 2 is true
    --# ** Note: c = "111"
    --# ** Note: c > "2" is false
    --# ** Note: c > "1" is true
    --# ** Note: d = "111"
    --# ** Note: d > "010" is true
     
    Mike Treseler, Jun 28, 2003
    #4
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