Strange FPGA problem

[williams]

Hello,

I am integrating an IP core and i am facing a strange problem.
One of the register of the IP core which is R/W register is not
writable ..in simulation I am able to write but when ported to FPGA I
am not able to write…its default value is also wrong and when I write
to one fixed register in that core... its value gets reflects on that
register. Reset value of all the register is ok and I am able to read
and write all R/W registers except one. What may be the
problem…..since simulation results shows that the IP is ok…so I cannot
pin point that tell the IP vendor that there is a bug in ur IP…..

Any feedback???
Thanks and Regards
Williams

 

[Egbert Molenkamp]

Sometimes a register in a register file has a constant value. E.g. R0 in the
MIPS is always 0.
http://www.web-ee.com/primers/files/MIPS/MIPS.htm

Maybe you have a similar problem
(hence your IP model is incorrect)

Egbert Molenkamp

 

[Navneet Rao]

Hi Williams:

If you are using Verilog: Check your port-width mismatches in the
instantiation(s)/wire(s)/reg(s) definitions. Even if verilog, does not
report above errors,
go through the synthesis report warnings in detail.

-Navneet

 

[Swapnajit Mittra]

Just a hunch, but this smells like a bitstream loading problem.
Perhaps your connection while loading the bitstream was not
OK. Try reloading the bitstream and check after that.

- Swapnajit.

 

[backhus]

Hi Williams,
have you made a timing simulation of the placed and routed design?
Maybe the write enable has a high delay for that one register, and
doesn't meet timing requirements anymore. (Just a guess)
Is your IP-core a softcore (only source) or a preplaced and wired hardmacro?

have a nice synthesis
Eilert