strange integer range

Discussion in 'VHDL' started by Salvatore Callea, Aug 26, 2004.

  1. Do you Know the way to create a discountinuous
    range of integer to use as index for a std_logic_vector
    array?
    I've tried to make:

    type disc_range is (7, 6, 5, 4, 3, 2, 1, 0);
    signal s1: std_logic_vector(disc_range);

    but the simulator gave me the error:
    near "7": expecting: CHAR IDENTIFIER

    Thanks in advance: Salvatore
    Salvatore Callea, Aug 26, 2004
    #1
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  2. Salvatore Callea <> wrote in
    news:Xns955174C3F689Dcalleaslabenit@130.133.1.4:

    > Do you Know the way to create a discountinuous
    > range of integer to use as index for a std_logic_vector
    > array?
    > I've tried to make:
    >
    > type disc_range is (7, 6, 5, 4, 3, 2, 1, 0);
    > signal s1: std_logic_vector(disc_range);
    >
    > but the simulator gave me the error:
    > near "7": expecting: CHAR IDENTIFIER
    >
    > Thanks in advance: Salvatore
    >




    Excuse for the error the range is (7, 6, 5, 2, 1, 0)
    Salvatore Callea, Aug 26, 2004
    #2
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  3. On 26 Aug 2004 10:14:05 GMT, Salvatore Callea
    <> wrote:

    >Salvatore Callea <> wrote in
    >news:Xns955174C3F689Dcalleaslabenit@130.133.1.4:
    >
    >> Do you Know the way to create a discountinuous
    >> range of integer to use as index for a std_logic_vector
    >> array?


    No, you can't do that.

    There are, of course, many possible ways to program around
    this problem. For example, you could create a constant
    array of integers mapping your discontinuous range on to
    a normal range.

    If you give some more details of your intended application,
    you may get some other interesting suggestions.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Aug 26, 2004
    #3
  4. Jonathan Bromley <> wrote in
    news::

    > On 26 Aug 2004 10:14:05 GMT, Salvatore Callea
    > <> wrote:
    >
    >>Salvatore Callea <> wrote in
    >>news:Xns955174C3F689Dcalleaslabenit@130.133.1.4:
    >>
    >>> Do you Know the way to create a discountinuous
    >>> range of integer to use as index for a std_logic_vector
    >>> array?

    >
    > No, you can't do that.
    >
    > There are, of course, many possible ways to program around
    > this problem. For example, you could create a constant
    > array of integers mapping your discontinuous range on to
    > a normal range.
    >
    > If you give some more details of your intended application,
    > you may get some other interesting suggestions.





    My purpose is to make registers with variable number and
    variable disposition of their bits.

    If I write:

    register_p: process(clk, rstn)
    begin
    if (rstn = '0') then
    q <= (others => '0');
    elsif (clk'event and clk = '1') then
    if (write = '1') then
    q <= data(q_range);
    end if;
    end if;
    end process;


    where I've defined:

    signal q : std_logic_vector(q_range);
    signal d : std_logic_vector(31 downto 0);

    Now, if I found the way to assign to q_range values like:

    1, 2, 3, 20, 22, 27, 28, 29, 30

    I don't re-write the process in case
    I've to add/subtract/change_position of bits
    inside the register. I only modify q_range!
    Salvatore Callea, Aug 27, 2004
    #4
  5. On 27 Aug 2004 08:04:50 GMT, Salvatore Callea
    <> wrote:



    >My purpose is to make registers with variable number and
    >variable disposition of their bits.
    >
    >register_p: process(clk, rstn)
    >begin
    > if (rstn = '0') then
    > q <= (others => '0');
    > elsif (clk'event and clk = '1') then
    > if (write = '1') then
    > q <= data(q_range);
    > end if;
    > end if;
    >end process;
    >
    >
    >where I've defined:
    >
    > signal q : std_logic_vector(q_range);
    > signal d : std_logic_vector(31 downto 0);
    >
    >Now, if I found the way to assign to q_range values like:
    >
    > 1, 2, 3, 20, 22, 27, 28, 29, 30
    >
    >I don't re-write the process in case
    >I've to add/subtract/change_position of bits
    >inside the register. I only modify q_range!


    OK. You have a collection of register bits and you
    want to map them to certain specific bits of a bus.

    The problem is: what does the definition of your
    collection of register bits look like? You are
    asking for it to be a "sparse array", with only some
    of its elements populated. This isn't possible in VHDL,
    but on the other hand if you create a full-width register
    and *use* only some of the bits, the unused bits will
    be optimised away by synthesis; so the question is
    not so much how to write to the bits, as how to
    read from them!

    Here's a suggestion for a possible way to code that
    kind of idea. Many details will need to be changed
    to suit your purposes, of course, but the key point
    is that it's easy to change the flag register bit
    assignments.

    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    Step 1:
    ~~~~~~~
    Define an enumeration type containing the flag names:

    type T_csr_names is (ENABLE, MODE, PAUSE);

    Step 2:
    ~~~~~~~
    Define a special type of std_logic_vector to hold the flags.
    It's like a std_logic_vector, but indexed by the flag names:

    type T_csr_reg is array(T_csr_names) of std_logic;

    Step 3:
    ~~~~~~~
    Define a constant to represent the mapping of flags to
    register bits in the memory map.

    type T_csr_bitmap is array(T_csr_names) of natural;
    constant csr_bitmap: T_csr_bitmap := (
    ENABLE => 13, -- ENABLE flag on bit 13
    MODE => 7, -- etc...
    PAUSE => 22 );


    Step 4:
    ~~~~~~~
    Implement the flag register.

    signal csr_reg: T_csr_reg;
    signal databus: std_logic_vector(31 downto 0);

    write_CSR : process (clock, reset)
    begin
    if reset = '1' then
    csr_reg <= (others => '0');
    elsif rising_edge(clock) then
    for flag in T_csr_names loop
    csr_reg(flag) <= databus(csr_bitmap(flag));
    end loop;
    end if;
    end process;

    readback_CSR : process (csr_reg, readback)
    begin
    if readback = '1' then
    databus => (others => '0'); --- or (others => '-')
    for flag in T_csr_names loop
    databus(csr_bitmap(flag)) <= csr_reg(flag);
    end loop;
    else
    databus <= (others => 'Z');
    end if;
    end process;

    Step 5:
    ~~~~~~~
    Get individual flag values out of your flag register,
    and into the specialised logic that uses them.

    enable_flag <= csr_reg(ENABLE);
    mode_flag <= csr_reg(MODE);
    pause_flag <= csr_reg(PAUSE);

    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    This scheme is quite easy to change if the flag register
    definition changes.

    To chnage bit assignments without changing the structure
    of the flag register itself, you need only change the
    definition of "constant csr_bitmap". This is quite
    similar to the "disjoint range" you wanted.

    To change the flags themselves, you need to change three
    things:
    (1) the definition of enumeration type T_csr_names
    (2) the bit mapping constant csr_bitmap
    (3) the code that makes use of the individual flag bits
    (Step 5 in my example) - but I don't think that's a
    problem, because these bits will be used in random
    logic in any case.

    Hope this is a little nearer to what you wanted.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Aug 27, 2004
    #5
  6. Thanks a lot, your solution is very good for my job

    Salvatore
    Salvatore Callea, Aug 27, 2004
    #6
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