strange VHDL syntax question

Discussion in 'VHDL' started by Michael Riepe, Oct 6, 2004.

  1. Hi everybody,

    this is something for the language experts out there.

    I know that it's legal to override implicitly declared operators (from a
    type declaration) with an explicit declaration, but is it also allowed
    to override an implicit _alias_ declaration of such an operator (as
    created by an alias declaration for the type)?

    That is, may I write something like this?

    package strange is
    alias mytype is bit;
    -- this implicitly declares, among others:
    -- alias "and" is std.standard."and" [ bit, bit return bit ];
    -- and now, declare a homograph:
    function "and" (l, r : mytype) return mytype;
    end strange;

    The standard isn't very clear about that, it just mentions that "an
    implicit declaration of a predefined operation" is overridden by a
    second homograph in the same declarative region.

    Thanks in advance,
    --
    Michael "Tired" Riepe <-hannover.de>
    "All I wanna do is have a little fun before I die"
    Michael Riepe, Oct 6, 2004
    #1
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  2. Michael Riepe <-hannover.de> wrote in message news:<ck1pjh$geg$-hannover.de>...

    > may I write something like this?
    >
    > package strange is
    > alias mytype is bit;
    > -- this implicitly declares, among others:
    > -- alias "and" is std.standard."and" [ bit, bit return bit ];


    An alias doen't declare anything except an
    alternate name for an existing identifier.
    See Ashenden 2ed pp 260-263.

    > -- and now, declare a homograph:
    > function "and" (l, r : mytype) return mytype;
    > end strange;


    Looks like you've overloaded the bit "and" function,
    but you are missing a package body.
    Try it on modelsim and see.

    What is you objective?

    -- Mike Treseler
    Mike Treseler, Oct 11, 2004
    #2
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