Structs in VHDL

Discussion in 'VHDL' started by Don Otknow, Mar 4, 2011.

  1. Don Otknow

    Don Otknow Guest

    Hello,

    I want to know if there is a way to group variables in VHDL that self-
    documents better than an array and allows for different types (IE the
    equivalent of a C struct). Is the record type this? Can one use
    signals and variables inside a record, and can a single record have
    both? Synthesis issues?

    Thanks,
    Don
     
    Don Otknow, Mar 4, 2011
    #1
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  2. On 3/4/2011 11:40 AM, Don Otknow wrote:

    > I want to know if there is a way to group variables in VHDL that self-
    > documents better than an array and allows for different types (IE the
    > equivalent of a C struct). Is the record type this?


    Yes, but not exactly.

    > Can one use
    > signals and variables inside a record,


    I can use a record variable inside a process or
    I can use a record signal inside an architecture.

    > and can a single record have
    > both?


    No. A record is *type* of signal, variable or constant.

    Synthesis issues?

    These are minimized by avoiding record type ports.
    Goggle comp.lang.vhdl. That subject has been beaten to death.

    -- Mike Treseler
     
    Mike Treseler, Mar 4, 2011
    #2
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  3. Don Otknow

    Tricky Guest


    >
    > Synthesis issues?
    >
    > These are minimized by avoiding record type ports.
    > Goggle comp.lang.vhdl. That subject has been beaten to death.
    >
    >           -- Mike Treseler


    Avoid record types for ports - since when? Maybe for inouts, but for
    single direction they are handy.
     
    Tricky, Mar 4, 2011
    #3
  4. On 5 Mrz., 08:44, Brian Drummond <> wrote:
    > Also avoid them for external (off-chip) ports. Synthesis etc will convert all
    > off-chip signals to std__logic[_vector]. Which makes dropping the post-synth
    > netlist into your testbench a pain, unless you create a wrapper to convert port
    > types.
    >
    > Other than these, I can't think of any synthesis issues.


    Synopsys DC converts all elements of the record into one array. No
    problem for small records, but it makes design handling quite hard, if
    your record is complex or nested and has some wide bus. I once had
    seen a record as Input that results in an array of more than 100 bits
    as Input after synthesis on top level of the design. Was no fun to
    collect adress, data and control signals out of this bus.

    bye Thomas
     
    Thomas Stanka, Mar 8, 2011
    #4
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