Structural VHDL - Accesing signals of instances

Discussion in 'VHDL' started by Valentin Tihomirov, Nov 1, 2003.

  1. I understand that entity defines inteface restricting the range of signals
    available for communication with instances of that entity. May be there is
    no much sense to bypass the restriction but I consider this opportunity to
    be used in test bench.


    uut: entity UART port map (
    .....
    );

    --stimulate uart


    --wait until transmitter is empty
    wait until uut.transmitter.busy = '0';

    -- go on
     
    Valentin Tihomirov, Nov 1, 2003
    #1
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  2. Valentin Tihomirov

    Jim Lewis Guest

    If you are using ModelSim, you can use the
    signal spy package.

    Cheers,
    Jim

    Valentin Tihomirov wrote:

    > I understand that entity defines inteface restricting the range of signals
    > available for communication with instances of that entity. May be there is
    > no much sense to bypass the restriction but I consider this opportunity to
    > be used in test bench.
    >
    >
    > uut: entity UART port map (
    > ....
    > );
    >
    > --stimulate uart
    >
    >
    > --wait until transmitter is empty
    > wait until uut.transmitter.busy = '0';
    >
    > -- go on
    >
    >
    >


    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Nov 1, 2003
    #2
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  3. Valentin Tihomirov wrote:

    > I understand that entity defines inteface restricting the range of
    > signals available for communication with instances of that entity.
    > May be there is no much sense to bypass the restriction but I
    > consider this opportunity to be used in test bench.


    Declare the signals you want to observe in a package and "use" that
    package both in the DUT and testbench. See also
    http://www.eda.org/comp.lang.vhdl/FAQ1.html#monitor

    Paul.
     
    Paul Uiterlinden, Nov 2, 2003
    #3
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