structural VHDL

[gg]

hi all,

I need to design a structural model of function unit (of a datapath) consisting of ALU and SHIFTER.
http://s9.postimg.org/tw3hivo7j/datapath_fn.png

As far as I know, a structural model is a code representing a block diagram of the system .. am I right?



Now... with a very basic knowledge I obtained,
I started by looking at the operations of both blocks in the function unit:
ALU - ADD, ADDC, SUB, SUBC, AND, OR, XOR, NOT
Shifter - ROR, ROL, RORC, ROLC

Now, to start with, I tackled the ALU alone by defining each component. Example shown for addition and or operation.
___
entity ALU is
port(A, B, c_in: in std_logic_vector(3 downto 0) ;
sum, c_out: out std_logic_vector(3 downto 0));
end entity ALU;

architecture structural of ALU is

component Adder is
port (x,y: in std_logic_vector(3 downto 0);
sum, carry: out std_logic);
end component Adder;

......

component or_1 is
port (x,y: in std_logic_vector(3 downto 0);
z : out std_logic);
end component or_1;
___

and finally component instantiation statements:
___

begin
Add_b: Adder port map(x=>A, y=>B, sum=>sum, carry=>c_out);
.....
Or_b: or_1 port map(x=>A, y=>B, z=>sum);
end architecture structural;
___


1. Am I on the right track?
2. Now I need to code the shifter as well ..

How should I go with it?