Study material for logic design

Discussion in 'VHDL' started by salah.kazi@gmail.com, Jan 9, 2006.

  1. Guest

    Hi All Verilog users:

    I am trying to find some study material to cover the basics of logic
    design. Actually I am preparing for an interview. Can anyone of you
    point to me some material online or forward me any documents that you
    have in some of the topics of logic design i.e.

    - Timing issues with a logic delay block sandwiched between two flip
    flops etc
    - Setup and hold time concepts and formulas
    - Metastability etc
    - General timing issues and faced in logic design synthesis

    Your feedback will be greatly appreciated.

    Regards,

    Salah
    salah.kazi @ gmail . com



    --
    Salahuddin (Salah) Kazi
    (416) 716-5634 (Cell), (905) 472-8890 (Home)
    Fax: (905) 201-8850,
    http://salahkazi.tripod.com/resume.htm
     
    , Jan 9, 2006
    #1
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  2. Charles, NG Guest

    One good paper which summarises many important issues is the actel HDL
    coding guide under
    http://www.actel.com/documents/hdlcode_ug.pdf

    I don't remember it doing much on metastability but that's easy enough
    to google for. If you have access to a library, one of the best sources
    I am aware of is the chapter in "High Speed Digital Design" by Johnson &
    Graham.

    Good luck in the interview.
     
    Charles, NG, Jan 9, 2006
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  3. Guest

    Thanks a lot Charles.

    Salah
     
    , Jan 11, 2006
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