subtype for integers

[Hari]

Hi,
I have been trying to subtype for integers in xilinx ISE (for eg.:
SUBTYPE WORD IS INTEGER RANGE -2**19 TO 2**19-1. But the problem is
when i try to simulate in modelsim, i get "fatal error in line ...",
though i am able to synthesis the code in Xilinx ISE.How do i fix this
problem.

Hari

 

[Egbert Molenkamp]

Hi,
I have been trying to subtype for integers in xilinx ISE (for eg.:
SUBTYPE WORD IS INTEGER RANGE -2**19 TO 2**19-1. But the problem is
when i try to simulate in modelsim, i get "fatal error in line ...",

Probably you perform arithmetic operation on a variable/signal of this
subtype and the results is out of the range of the subtyp; e.g.
(2**19-1)+1

Egbert Molenkamp

 

[Hari]

Probably you perform arithmetic operation on a variable/signal of this
subtype and the results is out of the range of the subtyp; e.g.
(2**19-1)+1

Egbert Molenkamp

Hi,
I don't think so the problem persists even when use zero as input.
Hari

 

[Egbert Molenkamp]

"Egbert Molenkamp" <[email protected]> wrote in message


Hi,
I don't think so the problem persists even when use zero as input.
Hari

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY funny IS
PORT (d: IN integer);
END;

ARCHITECTURE arch OF funny IS
SUBTYPE WORD IS INTEGER RANGE -2**19 TO 2**19-1;
signal w : word;
BEGIN
w <= d;
END arch;

You have probably a similar description as above.
The input d is of type integer.
Due to the initialization the initial value of d is integer'low (in
ModelSim -2147483648).
The range of subtype word is -524288 to 524287.

In this case you will get your error.

You can easily solve this in the entity:
ENTITY funny IS
PORT (d: IN integer := 0); -- now the initial vlaue is 0
END;

Egbert Molenkamp

 

[Hari]

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY funny IS
PORT (d: IN integer);
END;

ARCHITECTURE arch OF funny IS
SUBTYPE WORD IS INTEGER RANGE -2**19 TO 2**19-1;
signal w : word;
BEGIN
w <= d;
END arch;

You have probably a similar description as above.
The input d is of type integer.
Due to the initialization the initial value of d is integer'low (in
ModelSim -2147483648).
The range of subtype word is -524288 to 524287.

In this case you will get your error.

You can easily solve this in the entity:
ENTITY funny IS
PORT (d: IN integer := 0); -- now the initial vlaue is 0
END;

Egbert Molenkamp

Hi,
My code has something like:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY funny IS
PORT (d: IN std_logic_vector 15 downto 0;
d1: OUT std_logic_vector 15 downto 0);
END;

ARCHITECTURE arch OF funny IS
SUBTYPE WORD IS INTEGER RANGE -2**19 TO 2**19-1;
signal w : word;
BEGIN
w <= conv_integer(d);
d1<=conv_std_logic_vector(w,16);

END arch;

I tried initilaising with:
signal w : word:=0;
but still the probelm exsists.

Hari

 

[Jim Lewis]

The following works fine under ModelSim 5.7C.
I did switch you from synopsys packages to ieee packages.
I also made the IO signed.
To be really conservative (not required for ModelSim),
I put parentheses around -(2**19).
I also noted that W was correctly initialized with
the value: -52488, however, again to be conservative,
I initialized it to 0.

So try the following and if it does not work,
submit a bug report.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
ENTITY funny IS
PORT (
d: IN signed (15 downto 0);
d1: OUT signed (15 downto 0)
);
END;

ARCHITECTURE arch OF funny IS
SUBTYPE WORD IS INTEGER RANGE -(2**19) TO (2**19)-1;
signal w : word := 0;
BEGIN
w <= to_integer(d);
d1<= to_signed(w,16);

END arch;

Hi,
My code has something like:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY funny IS
PORT (d: IN std_logic_vector 15 downto 0;
d1: OUT std_logic_vector 15 downto 0);
END;

ARCHITECTURE arch OF funny IS
SUBTYPE WORD IS INTEGER RANGE -2**19 TO 2**19-1;
signal w : word;
BEGIN
w <= conv_integer(d);
d1<=conv_std_logic_vector(w,16);

END arch;

I tried initilaising with:
signal w : word:=0;
but still the probelm exsists.

Hari

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