Successive arithmetic operations within a process

[dennismccarty]

I'm trying to put multiple arithmetic arithmetic operations within a non-clocked process so that the result will be al combinatorial logic.

I can accept infered latches, but prefer not to have them.

The simulation does not work. A snipet of the code is as follows:

ARCHITECTURE behavior OF sq_root IS
signal q2 : std_logic_vector(1 downto 0);
--signal q3 : std_logic_vector(2 downto 0);
signal q4rem : std_logic_vector(3 downto 0);
--signal q5 : std_logic_vector(4 downto 0);
signal q6,q6rem,q6sub : std_logic_vector(5 downto 0);
signal q8,q8sub : std_logic_vector(7 downto 0);
--signal qfinal : std_logic_vector(7 downto 0);

BEGIN

process (d)
begin
if d(7) = '1' then --MSB of one. Start Calculation
y(3) <= '1';
q2 <= d(7 downto 6) - "01";

q4rem <= (q2 & (d(5 downto 4))) - "0101";

The subtraction for q2 evaluates correctly, but q4rem evaluates as unknown.
What is wrong?

 

[jeppe]

Try this addition to the sensitivity-list (but Im not sure you will succed)

process(d, q2)

Your welcome
Jeppe