Sum of array

Discussion in 'VHDL' started by VHDL_HELP, Mar 13, 2007.

  1. VHDL_HELP

    VHDL_HELP Guest

    hi every body,
    how calculate the sum of an array
    for example , i have an array of 4 elements and i want the sum ,
    please i wnt a solution ,please
    thank you
    VHDL_HELP, Mar 13, 2007
    #1
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  2. On 13 Mar 2007 04:15:13 -0700, "VHDL_HELP" <> wrote:

    >hi every body,
    >how calculate the sum of an array
    >for example , i have an array of 4 elements and i want the sum ,
    >please i wnt a solution ,please
    >thank you


    for example,

    sum := a(1) + a(2) + a(3) + a(4);

    Generalising this to arrays of other sizes is left as a trivial
    exercise for the student.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Mar 13, 2007
    #2
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  3. VHDL_HELP

    VHDL_HELP Guest

    On 13 mar, 13:05, Jonathan Bromley <>
    wrote:
    > On 13 Mar 2007 04:15:13 -0700, "VHDL_HELP" <> wrote:
    >
    > >hi every body,
    > >how calculate the sum of an array
    > >for example , i have an array of 4 elements and i want the sum ,
    > >please i wnt a solution ,please
    > >thank you

    >
    > for example,
    >
    > sum := a(1) + a(2) + a(3) + a(4);
    >
    > Generalising this to arrays of other sizes is left as a trivial
    > exercise for the student.
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    this is my vhdl program , it is corrct on syntax but not
    synthetisable

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity somme is
    Port ( clk : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR (3 downto 0);
    taille : in STD_LOGIC_VECTOR (2 downto 0);

    dout : out STD_LOGIC_VECTOR (3 downto 0)
    );
    end somme;

    architecture Behavioral of somme is
    type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal s : tab;
    begin
    process(clk)
    begin
    if clk'event and clk ='1' then
    s(conv_integer(taille)) <= din;
    end if;
    end process;
    dout <= s(0) + s(1) + s(2) + s(3);
    end Behavioral;
    VHDL_HELP, Mar 13, 2007
    #3
  4. VHDL_HELP schrieb:


    >> What was the problem for synthesis?


    > i dont find my result , the process cuts and i dont find my result


    What does it do?

    Did you simulate before synthesis? Overflow will occur easily using
    these bitwidths.

    Ralf
    Ralf Hildebrandt, Mar 13, 2007
    #4
  5. On 13 Mar 2007 08:56:48 -0700, "VHDL_HELP"
    <> wrote:


    >this is my vhdl program , it is corrct on syntax but not
    >synthetisable


    It looks synthesisable to me.
    What was the problem for synthesis?

    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Mar 13, 2007
    #5
  6. VHDL_HELP

    VHDL_HELP Guest

    On 13 mar, 17:04, Jonathan Bromley <>
    wrote:
    > On 13 Mar 2007 08:56:48 -0700, "VHDL_HELP"
    >
    > <> wrote:
    > >this is my vhdl program , it is corrct on syntax but not
    > >synthetisable

    >
    > It looks synthesisable to me.
    > What was the problem for synthesis?
    >
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    i dont find my result , the process cuts and i dont find my result
    VHDL_HELP, Mar 13, 2007
    #6
  7. On 13 Mar 2007 09:08:18 -0700, "VHDL_HELP"
    <> wrote:

    >> It looks synthesisable to me.
    >> What was the problem for synthesis?


    >i dont find my result , the process cuts and i dont find my result


    Works for me.... one 2-to-4 decoder, 16 flip-flops, three 4-bit
    full adders. Seems like you have a problem with usage of
    your synthesis tool. It's probably best for you to find a local
    expert to get started with your tools in your environment.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Mar 13, 2007
    #7
  8. VHDL_HELP

    VHDL_HELP Guest

    On 13 mar, 16:58, Ralf Hildebrandt <> wrote:
    > VHDL_HELP schrieb:
    >
    > >> What was the problem for synthesis?

    > > i dont find my result , the process cuts and i dont find my result

    >
    > What does it do?
    >
    > Did you simulate before synthesis? Overflow will occur easily using
    > these bitwidths.
    >
    > Ralf


    i have as result for dout : 4'hX as a result ===> it is a result for
    the simulation
    VHDL_HELP, Mar 13, 2007
    #8
  9. VHDL_HELP

    VHDL_HELP Guest

    On 13 mar, 17:20, Jonathan Bromley <>
    wrote:
    > On 13 Mar 2007 09:08:18 -0700, "VHDL_HELP"
    >
    > <> wrote:
    > >> It looks synthesisable to me.
    > >> What was the problem for synthesis?

    > >i dont find my result , the process cuts and i dont find my result

    >
    > Works for me.... one 2-to-4 decoder, 16 flip-flops, three 4-bit
    > full adders. Seems like you have a problem with usage of
    > your synthesis tool. It's probably best for you to find a local
    > expert to get started with your tools in your environment.
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    with this program , i have the same problem into simulation , please
    help me , i havent someone near to me that can give me help

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity somme is
    Port ( clk : in STD_LOGIC;
    reset : in std_logic;
    clk_out : out std_logic;
    din : in STD_LOGIC_VECTOR (3 downto 0);
    taille : in STD_LOGIC_VECTOR (2 downto 0);
    dout : out STD_LOGIC_VECTOR (3 downto 0)
    );
    end somme;

    architecture Behavioral of somme is
    type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal s : tab;
    begin
    process
    begin
    SEQ_LOOP:loop
    wait until clk'event and clk ='1';-- Au 1er front montant
    exit SEQ_LOOP when reset = '1';-- on met le front montant
    clk_out <= '1';-- celui d'horloge de sortie
    wait until clk'event and clk ='1';-- Au 2eme front montant
    exit SEQ_LOOP when reset = '1';-- on va lire
    s(0) <= din; -- le 1er element
    wait until clk'event and clk ='1';-- Au 2eme front montant
    exit SEQ_LOOP when reset = '1';-- on met le front descendant
    clk_out <= '0'; -- de sortie
    wait until clk'event and clk ='1';-- Au 3eme front montant
    exit SEQ_LOOP when reset = '1';-- on va lire
    s(1) <= din; -- le 2eme element
    wait until clk'event and clk ='1';-- Au 4eme front montant
    exit SEQ_LOOP when reset = '1';-- on met le front montant
    clk_out <= '1';-- celui d'horloge de sortie
    wait until clk'event and clk ='1';-- Au 4eme front montant
    exit SEQ_LOOP when reset = '1';-- on va lire
    s(2) <= din; -- le 3eme element
    wait until clk'event and clk ='1';-- Au 5eme front montant
    exit SEQ_LOOP when reset = '1';-- on met le front descendant
    clk_out <= '0'; -- de sortie
    wait until clk'event and clk ='1';-- Au 6eme front montant
    exit SEQ_LOOP when reset = '1';-- on va lire
    s(3) <= din; -- le 4eme element
    dout <= s(0) + s(1) + s(2) + s(3);
    end loop;
    end process;

    end Behavioral;
    VHDL_HELP, Mar 13, 2007
    #9
  10. VHDL_HELP schrieb:


    > i have as result for dout : 4'hX as a result ===> it is a result for
    > the simulation


    Behavioral or post-synthesis simulation?

    If there is X at the result, check the values of the array s, then check
    the value of the selector taille, then check the value of din, then
    check the value of the clock clk. Are there any other X?

    => Your problem is not the question if this description is synthesizable
    or not but the question where the X comes from. I guess there is
    something wrong with your testbench for this circuit.

    Ralf
    Ralf Hildebrandt, Mar 13, 2007
    #10
  11. VHDL_HELP

    VHDL_HELP Guest

    On 13 mar, 20:43, Ralf Hildebrandt <> wrote:
    > VHDL_HELP schrieb:
    >
    > > i have as result for dout : 4'hX as a result ===> it is a result for
    > > the simulation

    >
    > Behavioral or post-synthesis simulation?
    >
    > If there is X at the result, check the values of the array s, then check
    > the value of the selector taille, then check the value of din, then
    > check the value of the clock clk. Are there any other X?
    >
    > => Your problem is not the question if this description is synthesizable
    > or not but the question where the X comes from. I guess there is
    > something wrong with your testbench for this circuit.
    >
    > Ralf


    hi every body ,
    i want to say thank you for all of u and this program can do the sum
    that i want
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity som is
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    en : in STD_LOGIC_VECTOR (2 downto 0);
    clk_out : out STD_LOGIC;
    so : out STD_LOGIC_VECTOR (3 downto 0);
    sor : out STD_LOGIC_VECTOR (3 downto 0));
    end som;

    architecture Behavioral of som is
    TYPE TAB IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
    signal t:TAB;
    SIGNAL s:STD_LOGIC_VECTOR (3 downto 0):="0000";
    begin
    process
    begin
    seq:loop
    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '1';
    t(0) <= en;

    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '0';
    t(1) <= en;

    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '1';
    t(2) <= en;

    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '0';
    t(3) <= en;
    ----- Mettre les éléments de tableau en sortie
    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '1';

    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '0';

    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '1';

    wait until clk'event and clk = '1';
    exit seq when reset ='1';
    clk_out <= '0';

    end loop;
    if reset = '1' then
    clk_out <= '0';
    s <= '0' & t(0) + t(1) + t(2) + t(3);
    so <= s;
    end if;
    end process;
    end Behavioral;

    --- thank you again
    VHDL_HELP, Mar 19, 2007
    #11
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