sum of array

Discussion in 'VHDL' started by VHDL_HELP, Mar 13, 2007.

  1. VHDL_HELP

    VHDL_HELP Guest

    hi every body ,

    please please how to calculate the sum of an array ( for example an
    array of std_logic_vector(3 downto 0) )

    thank you
     
    VHDL_HELP, Mar 13, 2007
    #1
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  2. On 13 Mar 2007 06:22:17 -0700, "VHDL_HELP"
    <> wrote:

    >please please how to calculate the sum of an array ( for example an
    >array of std_logic_vector(3 downto 0) )


    This is the third time you have asked the same,
    very trivial, question. On one of the occasions I offered
    a frivolous (but correct) response.

    Which part of it have you already tried to do yourself?
    Which part of it do you find difficult?

    I don't expect any meaningful response, because the
    last time I gave a detailed answer to one of your
    questions you completely ignored it.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Mar 13, 2007
    #2
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  3. VHDL_HELP

    VHDL_HELP Guest

    On 13 mar, 14:48, Jonathan Bromley <>
    wrote:
    > On 13 Mar 2007 06:22:17 -0700, "VHDL_HELP"
    >
    > <> wrote:
    > >please please how to calculate the sum of an array ( for example an
    > >array of std_logic_vector(3 downto 0) )

    >
    > This is the third time you have asked the same,
    > very trivial, question. On one of the occasions I offered
    > a frivolous (but correct) response.
    >
    > Which part of it have you already tried to do yourself?
    > Which part of it do you find difficult?
    >
    > I don't expect any meaningful response, because the
    > last time I gave a detailed answer to one of your
    > questions you completely ignored it.
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    hi im sorry really sorry ,
    first off all i did repeat the same question coz it apprear late on
    the discussions
    what i did is :
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity somme is
    Port ( clk : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR (3 downto 0);
    taille : in STD_LOGIC_VECTOR (2 downto 0);

    dout : out STD_LOGIC_VECTOR (3 downto 0)
    );
    end somme;

    architecture Behavioral of somme is
    type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal s : tab;
    begin
    process(clk)
    begin
    if clk'event and clk ='1' then
    s(conv_integer(taille)) <= din;
    end if;
    end process;
    dout <= s(0) + s(1) + s(2) + s(3);
    end Behavioral;


    -------------------------------------------------------------------------------------------------------------------
    it is correct with syntax but not synthetisable , i want a clear idea
    that means how to think with a correct way
    sorry again and i didnt mean to nelgect your anwsers but i m working
    to find solutions
     
    VHDL_HELP, Mar 13, 2007
    #3
  4. Mike Treseler, Mar 13, 2007
    #4
  5. VHDL_HELP

    D Stanford Guest

    > architecture Behavioral of somme is
    > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
    > signal s : tab;
    > begin
    > process(clk)
    > begin
    > if clk'event and clk ='1' then
    > s(conv_integer(taille)) <= din;
    > end if;
    > end process;
    > dout <= s(0) + s(1) + s(2) + s(3);
    > end Behavioral;
    >



    You're problem is probably in using the signal taille as an index into
    s. Instead, use taille in a case statement, or as a selector for a
    demux.
     
    D Stanford, Mar 13, 2007
    #5
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