swapping bits in a byte

Discussion in 'VHDL' started by Konstantin Kletschke, Apr 4, 2007.

  1. Hi Folks!

    We have an XC2C64A cpld here. It is used as a bit more complex Bus
    buffer, lets say an enhanced 74xx245 :)
    It is buffering the lower (D0 - D7) of the databus from 1.8V to 3V
    side.
    Now we realized one Chip selected by CS4 is connected with its bits
    swapped :-(

    D0 - D7
    D1 - D6
    ....
    D7 - D0

    Now we realize that we are too stupid to pimp our exisiting

    p18_MD(7 downto 0) <= p33_DATA(7 downto 0) when ( ... )

    (the omitted ( ... ) part is mainly bus logic including the
    chipselects.)

    We need to do an extra part for that regarding CS4, thats clear, but
    how do we mirror the data bits in a most efficient manner?

    Kind Regards, Konsti
     
    Konstantin Kletschke, Apr 4, 2007
    #1
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  2. Konstantin Kletschke

    Andy Guest

    You can try declaring one of the ports with the reverse range, i.e.
    instead of (7 downto 0), use (0 to 7). and then assign as follows:

    p18_md <= p33_data when ...

    If you are assigning and/or referencing the entire vector, there is no
    need to explicitly specify the range (whether you are reversing the
    connection or not).

    Vector assignments are made bitwise, left to right, regardless of
    indexing. However you cannot specify a range on a vector that is the
    reverse of the direction with which that vector was declared.

    But check your final pinout, since some tools seem to have problems
    with reversed range declarations on ports.

    If that does not work, write and use a function with a loop to reverse
    the bits. Something like:

    function reverse_bits (arg: std_logic_vector) return std_logic_vector
    is
    variable result: std_logic_vector(arg'reverse_range);
    begin
    for i in arg'range loop
    result(i) := arg(i);
    end loop;
    return result;
    end reverse_bits;

    Then you can assign:

    p18_md <= reverse_bits(p33_data) when ...

    Andy



    On Apr 4, 9:50 am, Konstantin Kletschke <> wrote:
    > Hi Folks!
    >
    > We have an XC2C64A cpld here. It is used as a bit more complex Bus
    > buffer, lets say an enhanced 74xx245 :)
    > It is buffering the lower (D0 - D7) of the databus from 1.8V to 3V
    > side.
    > Now we realized one Chip selected by CS4 is connected with its bits
    > swapped :-(
    >
    > D0 - D7
    > D1 - D6
    > ...
    > D7 - D0
    >
    > Now we realize that we are too stupid to pimp our exisiting
    >
    > p18_MD(7 downto 0) <= p33_DATA(7 downto 0) when ( ... )
    >
    > (the omitted ( ... ) part is mainly bus logic including the
    > chipselects.)
    >
    > We need to do an extra part for that regarding CS4, thats clear, but
    > how do we mirror the data bits in a most efficient manner?
    >
    > Kind Regards, Konsti
     
    Andy, Apr 4, 2007
    #2
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  3. Konstantin Kletschke

    Dave Pollum Guest

    On Apr 4, 9:50 am, Konstantin Kletschke <> wrote:
    > Hi Folks!
    >
    > We have an XC2C64A cpld here. It is used as a bit more complex Bus
    > buffer, lets say an enhanced 74xx245 :)
    > It is buffering the lower (D0 - D7) of the databus from 1.8V to 3V
    > side.
    > Now we realized one Chip selected by CS4 is connected with its bits
    > swapped :-(
    >
    > D0 - D7
    > D1 - D6
    > ...
    > D7 - D0
    >
    > Now we realize that we are too stupid to pimp our exisiting
    >
    > p18_MD(7 downto 0) <= p33_DATA(7 downto 0) when ( ... )
    >
    > (the omitted ( ... ) part is mainly bus logic including the
    > chipselects.)
    >
    > We need to do an extra part for that regarding CS4, thats clear, but
    > how do we mirror the data bits in a most efficient manner?
    >
    > Kind Regards, Konsti


    1)
    signal data : std_logic_vector(7 downto 0);
    signal cs4_data : std_logic_vector(7 downto 0);
    ....
    data(7 downto 0) <= cs4_data(0 to 7);

    2) Or as Andy suggested:
    signal data : std_logic_vector(7 downto 0);
    signal cs4_data : std_logic_vector(0 to 7);
    ....
    data <= cs4_data;

    -Dave Pollum
     
    Dave Pollum, Apr 7, 2007
    #3
  4. Konstantin Kletschke

    Andy Guest

    On Apr 7, 8:49 am, "Dave Pollum" <> wrote:
    > On Apr 4, 9:50 am, Konstantin Kletschke <> wrote:
    >
    >
    >
    > > Hi Folks!

    >
    > > We have an XC2C64A cpld here. It is used as a bit more complex Bus
    > > buffer, lets say an enhanced 74xx245 :)
    > > It is buffering the lower (D0 - D7) of the databus from 1.8V to 3V
    > > side.
    > > Now we realized one Chip selected by CS4 is connected with its bits
    > > swapped :-(

    >
    > > D0 - D7
    > > D1 - D6
    > > ...
    > > D7 - D0

    >
    > > Now we realize that we are too stupid to pimp our exisiting

    >
    > > p18_MD(7 downto 0) <= p33_DATA(7 downto 0) when ( ... )

    >
    > > (the omitted ( ... ) part is mainly bus logic including the
    > > chipselects.)

    >
    > > We need to do an extra part for that regarding CS4, thats clear, but
    > > how do we mirror the data bits in a most efficient manner?

    >
    > > Kind Regards, Konsti

    >
    > 1)
    > signal data : std_logic_vector(7 downto 0);
    > signal cs4_data : std_logic_vector(7 downto 0);
    > ...
    > data(7 downto 0) <= cs4_data(0 to 7);
    >
    > 2) Or as Andy suggested:
    > signal data : std_logic_vector(7 downto 0);
    > signal cs4_data : std_logic_vector(0 to 7);
    > ...
    > data <= cs4_data;
    >
    > -Dave Pollum


    #1 won't work, since it is not legal VHDL. You cannot specify a range
    on an object that is the reverse direction of how the object was
    declared.

    Andy
     
    Andy, Apr 9, 2007
    #4
  5. How about using a simple mux?

    err, in a process create

    if cs4_sel = '1' then
    data <= data_swapped_around;
    else
    data <= data_not_swapped_arround;
    end if;

    then inside your code tie the data_swapped_around to the pins as required by
    the chip on CS4, data_not_swapped_around should be connected to the original
    data.

    You'll have to make sure you don't violate any timing requirements with the
    added latency of a mux though.

    or if you need a fully synchronous design you might add a register on the
    output. Even so, I think an eight bit mux is pretty compact for a CPLD.

    Ben
     
    Benjamin Todd, Apr 10, 2007
    #5
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