switch design on fpga

Discussion in 'VHDL' started by hema, Oct 9, 2006.

  1. hema

    hema Guest

    hiiii,

    In case of designing the switch controller on FPGA ,how to resolve the
    contention when all the input buffers(FIFO) try out for the same output
    FIFO????

    regards,
    hema.
     
    hema, Oct 9, 2006
    #1
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  2. hema

    KJ Guest

    "hema" <> wrote in message
    news:...
    > hiiii,
    >
    > In case of designing the switch controller on FPGA ,how to resolve the
    > contention when all the input buffers(FIFO) try out for the same output
    > FIFO????


    An arbitrator.

    KJ
     
    KJ, Oct 9, 2006
    #2
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