switch to verilog module in a vhdl wrapper

Discussion in 'VHDL' started by elfanch, Nov 18, 2009.

  1. elfanch

    elfanch

    Joined:
    Nov 18, 2009
    Messages:
    1
    Hello,

    I have a vhdl wrapper which instantiates a component called FGH. For this FGH I have a verilog and a vhdl module. I would like to compare simulation performance of both. I wish I could switch from one to the other model without changing the wrapper (as in fact it's a full library I would like to switch from vhdl to verilog…).

    I got a problem with some parameters :

    For INIT parameter, with the default modules :

    Verilog :
    module FGH (O, I0, I1, I2, I3, I4);

    parameter INIT = 8'hAA;
    ...
    and

    Vhdl :
    component FGH
    generic (
    INIT : bit_vector := X"AA"
    );
    ..

    I get a type mismatch for INIT, when instanciating the verilog module.

    If I update the vhdl component like this :
    component FGH
    generic(
    INIT : integer := 170
    );

    I no longer get the mismatch error, but the X"BB" that is used in instanciation is not understood (bit string literal found when non-array std.standard.integer was expected.

    FGH_1 : FGH
    generic map(
    INIT => X"BB"
    )


    To fix this I have to change the instanciation to : INIT => 187

    But I am no longer able to swithc back to the vhdl model without error…

    Would someone have an idea of this?

    Thank you very much
    elfanch, Nov 18, 2009
    #1
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