sychronize outside signal

Discussion in 'VHDL' started by Arron, Nov 11, 2004.

  1. Arron

    Arron Guest

    In my project, the main clock is 10MHz and the input signal is a 1kHz
    square wave. I hope to detect the rising edge of the input signal and
    output a high level voltage for one clock when it were detected. I use
    finite state machine to realize the design in Altera Quartus II, the
    simulation is OK. But the hardware (Cyclone) gives unexpected results:
    no output or several clock signals after the rising edge of input
    signal. Does anybody know other method to my project? Thank you in
    advance.
     
    Arron, Nov 11, 2004
    #1
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  2. Arron

    Mark Guest

    Are you using a re-synchronizer (two or more back to back flip flops)
    on the incoming signal or merely sending it straight into the state
    machine as an input?

    It sounds as though your circuit could be suffering from
    metastability.

    http://klabs.org/richcontent/General_Application_Notes/mestablestates/xilinx_metastable_recovery.pdf

    Try re-synchronising the signal first. The remaining logic for a
    rising ede detect is then trivial.

    (Arron) wrote in message news:<>...
    > In my project, the main clock is 10MHz and the input signal is a 1kHz
    > square wave. I hope to detect the rising edge of the input signal and
    > output a high level voltage for one clock when it were detected. I use
    > finite state machine to realize the design in Altera Quartus II, the
    > simulation is OK. But the hardware (Cyclone) gives unexpected results:
    > no output or several clock signals after the rising edge of input
    > signal. Does anybody know other method to my project? Thank you in
    > advance.
     
    Mark, Nov 11, 2004
    #2
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  3. Arron

    ALuPin Guest

    (Arron) wrote in message news:<>...
    > In my project, the main clock is 10MHz and the input signal is a 1kHz
    > square wave. I hope to detect the rising edge of the input signal and
    > output a high level voltage for one clock when it were detected. I use
    > finite state machine to realize the design in Altera Quartus II, the
    > simulation is OK. But the hardware (Cyclone) gives unexpected results:
    > no output or several clock signals after the rising edge of input
    > signal. Does anybody know other method to my project? Thank you in
    > advance.


    Hi,

    can you give some essential parts of your code to see what
    could go wrong?

    Rgds
    André
     
    ALuPin, Nov 11, 2004
    #3
  4. Arron

    Niv Guest

    "Arron" <> wrote in message
    news:...
    > In my project, the main clock is 10MHz and the input signal is a 1kHz
    > square wave. I hope to detect the rising edge of the input signal and
    > output a high level voltage for one clock when it were detected. I use
    > finite state machine to realize the design in Altera Quartus II, the
    > simulation is OK. But the hardware (Cyclone) gives unexpected results:
    > no output or several clock signals after the rising edge of input
    > signal. Does anybody know other method to my project? Thank you in
    > advance.


    As already stated, you may have metastability issues.
    Try this:

    SIGNAL reg1: STD_LOGIC;
    SIGNAL reg2: STD_LOGIC;
    SIGNAL reg3: STD_LOGIC;

    sync_1khz: PROCESS (reset_n, clk_1mhz)
    BEGIN
    IF reset_n = '0' THEN
    reg1 <= '0';
    reg2 <= '0';
    ELSIF rising_edge(clk_1mhz) THEN

    -- Insert metastability regs;

    reg1 <= in_1khz;
    reg2 <= reg1;
    reg3 <= reg2;

    -- Now detect the edge.

    IF reg2 = '1' AND reg3 = '0' THEN -- This is the 1KHz rising edge,
    delayed by a few 1MHz clock cycles.

    -- Do whatever with edge.

    END IF;
    END IF;

    END PROCESS sync_1khz;
     
    Niv, Nov 13, 2004
    #4
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