Syetem time in VHDL?

Discussion in 'VHDL' started by Trickyhead@gmail.com, Mar 15, 2007.

  1. Guest

    Is there any way of accessing the system time (not current simulation
    time) in VHDL?

    an example: when running a test bench, I generate a log file. I dont
    want to have to manually move this log file for storage before I run
    it again, so I want to put a time stamp in the name of the log file
    (so the previous one doesnt get overwritten).

    Would the only way to do this be to run the testbench externally (eg.
    via TCL) that passes the timestamp (or other meaningful name) in as a
    generic?
     
    , Mar 15, 2007
    #1
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  2. wrote:
    > Is there any way of accessing the system time (not current simulation
    > time) in VHDL?

    ....
    > Would the only way to do this be to run the testbench externally (eg.
    > via TCL) that passes the timestamp (or other meaningful name) in as a
    > generic?


    Either that or pass the timestamp from
    the unix/dos command line.

    -- Mike Treseler
    >
     
    Mike Treseler, Mar 15, 2007
    #2
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  3. HT-Lab Guest

    <> wrote in message
    news:...
    > Is there any way of accessing the system time (not current simulation
    > time) in VHDL?
    >
    > an example: when running a test bench, I generate a log file. I dont
    > want to have to manually move this log file for storage before I run
    > it again, so I want to put a time stamp in the name of the log file
    > (so the previous one doesnt get overwritten).
    >
    > Would the only way to do this be to run the testbench externally (eg.
    > via TCL) that passes the timestamp (or other meaningful name) in as a
    > generic?


    TCL is indeed the simplest way, most simulators have a full Tcl interpreter
    build in so you can just pass on the date as a generic (e.g. in Modelsim
    look up the vsim -G command line argument). Alternatively just parse your
    source file and modify the filename before running it, this might help you
    out http://www.ht-lab.com/freeutils/date2hdl/date2hdl.htm

    Hans
    www.ht-lab.com
     
    HT-Lab, Mar 15, 2007
    #3
  4. On Mar 15, 3:27 pm, wrote:
    > Is there any way of accessing the system time (not current simulation
    > time) in VHDL?
    >
    > an example: when running a test bench, I generate a log file. I dont
    > want to have to manually move this log file for storage before I run
    > it again, so I want to put a time stamp in the name of the log file
    > (so the previous one doesnt get overwritten).
    >
    > Would the only way to do this be to run the testbench externally (eg.
    > via TCL) that passes the timestamp (or other meaningful name) in as a
    > generic?


    Few years back I had this same issue and found few solutions. I even
    wrote a FAQ page, but then my PC crashed and I lost the data. I also
    changed my web hoster and lost some data in transition - yeah I'm not
    a big time HTML guru. Thanks to archive.org, I found this at:

    http://web.archive.org/web/20031220040057/http://www.noveldv.com/verif/hdl_faq/index.html

    Specifically, read:

    http://web.archive.org/web/20031220040057/http://www.noveldv.com/verif/hdl_faq/FAQ00007.htm

    I do intend to put that back on my page when time permits..

    Regards
    Ajeetha, CVC
    www.noveldv.com
     
    Ajeetha (www.noveldv.com), Mar 16, 2007
    #4
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