Sync high freq to 100Hz?

Discussion in 'VHDL' started by nivparsons, Feb 16, 2012.

  1. nivparsons

    nivparsons Guest

    I have a counter running at 2^20 HZ, driven by a clock about 100 times
    faster. (Osc_1)
    I also have an incoming rerference pulse every 10ms. (Osc 2 derived)

    I'd like to sync my fast counter so that it agrees with the reference,
    but freq too low for a PLL or DCM etc.
    So far, I have 2 counters, cntr_1 effectively assumes the time for
    10ms increments and then counts at the 2^20 rate. cntr_2, the one
    Ineed to sync, free runs, but is compared every sync pulse (just
    after) withthe updated cntr_1. The prescaler for cntr_2 is then incr
    or decr by 1 so it slows down or speeds up until it is close (1/2 lsb,
    I have extra bits) to cntr_1 value.

    This works, but if Ilose the 10ms sync pulses, then both cntrs free
    run, whereupon any drift due to clock freq diffs, in osc1 and osc2,
    will accumulate.

    I can't "pull" the oscillator (osc1) unfortunately, otherwise a simple
    solution presents itself.

    Is there a better way?

    Niv.
    nivparsons, Feb 16, 2012
    #1
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  2. nivparsons

    jeppe

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    jeppe, Feb 16, 2012
    #2
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  3. nivparsons

    KJ Guest

    On Feb 16, 1:54 pm, nivparsons <> wrote:
    >
    > This works, but if Ilose the 10ms sync pulses, then both cntrs free
    > run, whereupon any drift due to clock freq diffs, in osc1 and osc2,
    > will accumulate.
    >
    > I can't "pull" the oscillator (osc1) unfortunately, otherwise a simple
    > solution presents itself.
    >
    > Is there a better way?
    >


    Based on the actual clock frequencies, you can precompute what you
    expect your error will be once you're locked on, maybe it's +/- 0.5 or
    maybe it will be 0.67. In any case, once the expected 10 ms time
    expires if you don't receive a reference pulse within some expected
    window of time then you have come 'unlocked' and you can manually
    adjust it by the amount from that precomputed error.

    So if your expected error is 0.5, then you would adjust up by 1 after
    one 10 ms period, then adjust down by 1 on the next. Similarly, if it
    was 0.67, then two out of every three 10 ms periods you would adjust
    one way, the other time you would adjust the opposite way.

    Assuming you lose lock after you have fully locked on in the first
    place, then all you can do is adjust for the known error as best you
    can.

    Kevin Jennings
    KJ, Feb 17, 2012
    #3
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