synchronous register

Discussion in 'VHDL' started by ejann, Feb 10, 2009.

  1. ejann

    ejann

    Joined:
    Feb 10, 2009
    Messages:
    2
    Hi,

    Can someone show me how to;

    1. create a synchronous register set and reset signals that will output a toogle value for every clock pulse.

    2. create a counter with asynchronous reset and a load enable signals.This load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to the value of the number loaded.

    I'm using Altera Quartus II 8.1.

    Thanks.
     
    ejann, Feb 10, 2009
    #1
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  2. ejann

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    I am quite sure someone can show you how to do the two things you ask. I doubt if anyone will show you. This appears to be a student problem that you want someone else to solve for you. Niether one of the problems is difficult, so why don't you try to solve them yourself? There are many textbook illustrations of modules similar to what you want. Have you looked for any of them? If you try to solve them and don't quite do so, then show us what you tried and someone will point you in the right direction. I have never understood how a student expects to learn by being spoon fed answers that he/she is too lazy to even try to work out for himself/herself.
     
    eliascm, Feb 10, 2009
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  3. ejann

    ejann

    Joined:
    Feb 10, 2009
    Messages:
    2
    for Q1.

    library ieee;
    use ieee.std_logic_1164.all;

    entity shift is
    port(C, SI : in std_logic;
    SO : out std_logic);
    end shift;
    architecture beh of shift is
    signal tmp: std_logic_vector(7 downto 0);
    begin
    process (C)
    begin
    if (C'event and C='1') then
    for i in 0 to 6 loop
    tmp(i+1) <= tmp(i);
    end loop;
    tmp(0) <= SI;
    end if;
    end process;
    SO <= tmp(7);
    end beh;

    for Q2.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;

    entity count2 is
    port(clk,r,le : in std_logic;
    d : in integer;
    q : out integer);

    end count2;

    architecture beh of count2 is
    begin
    process(clk,r,le)
    variable var_cnt : integer range 0 to 256;

    begin
    case(r) is
    when '1' =>
    var_cnt :=0;
    when '0' =>
    if le ='1' then
    var_cnt :=d;
    elsif (clk'event and clk ='1') then
    var_cnt := var_cnt +1;
    end if;
    when others =>
    var_cnt := 0;
    end case;

    q<=var_cnt;

    end process;
    end beh;

    someone can verify that for me..
     
    ejann, Feb 11, 2009
    #3
  4. ejann

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Verify Code

    You should now make a test bench to simulate your code. That is the best way to ascertain that your design is functionally correct (it will also flag any syntax errors).
     
    eliascm, Feb 11, 2009
    #4
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