Hi,
Can someone show me how to;
1. create a synchronous register set and reset signals that will output a toogle value for every clock pulse.
2. create a counter with asynchronous reset and a load enable signals.This load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to the value of the number loaded.
I'm using Altera Quartus II 8.1.
Thanks.
Can someone show me how to;
1. create a synchronous register set and reset signals that will output a toogle value for every clock pulse.
2. create a counter with asynchronous reset and a load enable signals.This load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to the value of the number loaded.
I'm using Altera Quartus II 8.1.
Thanks.