Synchronous Signals

[Patrick]

Hello,

I've to read a signal (data rate : 4Mbps) and his clock (4MHz) with a
sampling clock of 88 MHz.

But when I visualize these signals they are not synchronous !!

I use this code :

ECHANT_IN : process (clk_bit_in,reset)
begin
if reset='1' then
data_clk_bit <= '0';
elsif (clk_bit_in'event and clk_bit_in='1') then
data_clk_bit <= data_in;
end if;
end process ECHANT_IN;

ECHANT_IN_2 : process (clock_smp,reset)
begin
if reset='1' then
clock_bit <= '0';
data <= '0';
elsif (clock_smp'event and clock_smp='1') then
clock_bit <= clk_bit_in;
data <= data_clk_bit;
end if;
end process ECHANT_IN_2;

 

[Jonathan Bromley]

I've to read a signal (data rate : 4Mbps) and his clock (4MHz) with a
sampling clock of 88 MHz.

But when I visualize these signals they are not synchronous !!

I use this code :

[snip]

If you are using an oversampling clock, why is it
appropriate to resynchronise your input data to
the input clock before sampling it?

Please describe:
- the timing specification of the input data and clock,
- what you are trying to achieve
and we will try to help.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Thomas Stanka]

But when I visualize these signals they are not synchronous !!

The second process generates the clock of the first process with 88
MHz oversampling of 4 MHz. Due to gate delay of the ff and signal
delay you will have a phase shift between 88MHz and "internal" 4 MHz.

I would expect your code to work fine even with this phase shift as
long, as the data signal switches far away from the rising edge of 4
MHz rising edge.
As you add some additional phase shift to your internal data due to
the gate delay of the register data_clk_bit and the signal delay to
the register data. Additional you will likely have some problems du to
metastability if the path from register clk_bit to register data via
data_clk_bit isn't shorter than 11 ns.
____ ____
Clk_4 ____| |_____| |____
_________ __________ ____
Data_good _________X__________X____
______ _________ ________
Data_bad ______X_________X________


bye Thomas

 

[Patrick]

I have a data signal (data) and his clock (data_clk : 4 MHz).

I would like to sampling these signal with an sampling clock (clk_smp : 88 MHz).

But this clock (clk_smp) is not synchronous with data_clk !!

I don't want to use a PLL.

It's what is doing an USART (Universal Synchronous ...)

How to do ?

thanks

 

[Jonathan Bromley]

I have a data signal (data) and his clock (data_clk : 4 MHz).
I would like to sampling these signal with an sampling clock (clk_smp : 88 MHz).
But this clock (clk_smp) is not synchronous with data_clk !!
I don't want to use a PLL.
It's what is doing an USART (Universal Synchronous ...)
How to do ?

1. Sample both data and data_clk using the oversampling clk_smp.
Now both these signals are synchronised to clk_smp.
2. Use the synchronised version of data_clk to identify the
correct moment for sampling the data.

For Step 2 you need to know the timing of data relative to
data_clk, and you have not told me that. Let me *guess* that
the correct sampling moment is at the falling edge of data_clk.
Then...

signal
-- INTERNAL SIGNALS
syn_data, -- incoming data resynchronised to 88MHz
syn_data_clk, -- incoming clock resynchronised to 88MHz
syn_data_clk_d, -- syn_data_clk delayed by one 88MHz cycle
-- OUTPUTS TO OTHER LOGIC, FULLY SYNCHRONOUS WITH 88MHz CLOCK
new_bit_available, -- asserted for one cycle: bit enable
new_bit_data: -- captured, resynchronised input data
std_logic;

....

process (clk_smp)
begin
if rising_edge(clk_smp) then
-- Capture synchronised versions of input data and clock
syn_data <= data;
syn_data_clk <= data_clk;
-- Get delayed version of syn_data_clk for edge detection
syn_data_clk_d <= syn_data_clk;
-- Clock edge detection
new_bit_available <= '0'; -- default
if syn_data_clk_d = '1' and syn_data_clk = '0' then
-- It's time to take a sample!
new_bit_available <= '1';
new_bit_data <= syn_data;
end if;
end if; -- rising_edge(clk_smp)
end process;

For extra credit:
- re-code my process so that all the internal flip-flops
are VHDL variables local to the process
- use your 88MHz oversampling to create a majority-voting
glitch filter on both clock and data
- add an additional input flip-flop on both clock and data
to reduce metastability risk
- add programmable sampling point, specified as a count of
88MHz cycles, so that sampling of data can be offset
from edges of data_clk

For lots of extra credit:
- automate the choice of sampling point offset, by
examining the position of data transitions and locating
the sampling point midway between transitions

Welcome to the wonderful world of multiple clock domains.
You have it pretty easy - your sampling clock is more than
20 times faster than your data rate. Things get harder
if that number is much smaller.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.