synopsys DC synthesis errors

Discussion in 'VHDL' started by chinski, Sep 22, 2008.

  1. chinski

    chinski

    Joined:
    Sep 22, 2008
    Messages:
    1
    hi,

    i'm currently trying to synthesize a design in Synopsys DC. the RTL codes have been verified using NCLaunch, and we're sure they are working properly. We tried simulating (using NCLaunch) after synthesis and the synthesized design seems to be outputting wrong data after a set number of clock cycles. We're sure we haven't missed any blocks in the .tcl file, and we're not getting any errors while synthesizing. Can someone give us an idea on what we can do to solve this problem?

    -chinski
    chinski, Sep 22, 2008
    #1
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