Synopsys & VHDL: **FFGEN**

[Sebastian Becker]

Hi NG,

i'm trying to get Synopsys to "compile" a behavioural description of a FSM
(some sort of 8-bit shift register) to a structural description (synthese).
Running the design optimization i only get **FFGEN** instead of "real" flip
flops... can anybody give me a hint why this doesn't work?

Thanks, Sebastian

VHDL-Description:
-------------------
PACKAGE my_types IS
TYPE CtlTyp IS (fHLT,fSHL,fSAL,fROL,fRCL);
END my_types;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.my_types.ALL;

ENTITY SReg8 IS
PORT(clk,load,reset,cin : IN Bit;
control : IN CtlTyp;
datain : IN Bit_Vector(7 DOWNTO 0);
dataout : OUT Bit_Vector(7 DOWNTO 0);
cout : OUT Bit);
END SReg8;

ARCHITECTURE beh1 OF SReg8 IS
SIGNAL AktReg, NextReg:Bit_Vector(8 DOWNTO 0);

BEGIN
PROCESS(clk,reset,load,datain,cin)
BEGIN
IF reset = '1' THEN
AktReg<="000000000";
ELSIF load = '1' THEN
AktReg <= cin & datain(7 DOWNTO 0);
ELSIF (clk'EVENT AND clk ='1') THEN
AktReg <= NextReg;
END IF;
END PROCESS;

PROCESS(AktReg,control)
BEGIN
CASE control IS
WHEN fHLT => NextReg <= AktReg;
WHEN fSAL => NextReg <= AktReg(7 DOWNTO 0) & AktReg(0);
WHEN fSHL => NextReg <= AktReg(7 DOWNTO 0) & '0';
WHEN fROL => NextReg <= AktReg(8) & AktReg(6 DOWNTO 0) & AktReg(7);
WHEN fRCL => NextReg <= AktReg(7 DOWNTO 0) & AktReg(8);
WHEN OTHERS => NextReg <= AktReg;
END CASE;
END PROCESS;

PROCESS(AktReg)
BEGIN
dataout <= AktReg(7 DOWNTO 0);
cout <= AktReg(8);
END PROCESS;
END ARCHITECTURE;

 

[Sebastian Becker]

Hi,

doing some more examination i found out that when i drop out these two lines
(parallel load function), it works (i get synthetisized FD2 flip flops).
i just don't get why?!

ELSIF load = '1' THEN
AktReg <= cin & datain(7 DOWNTO 0);

Sebastian

 

[Ansgar Bambynek]

Hi Sebastian,

the problem is the asynchronous load to your ffs.
This would result in a flipflop with asynchronous reset, asynchronous load
and a triggering clock. I',m not sure which library has been mapped for
synthesis but I doubt that such a ff is available.
Try to make your load synchronous, i.e.

BEGIN
PROCESS(clk,reset)
BEGIN
IF reset = '1' THEN
AktReg<="000000000";
ELSIF (clk'EVENT AND clk ='1') THEN
IF load = '1' THEN
AktReg <= cin & datain(7 DOWNTO 0);
ELSE
AktReg <= NextReg;
END IF;
END IF;
END PROCESS;

HTH

Ansgar

 

[Sebastian Becker]

Hi,

I thought the FD3 has asynchronous RESET and SET Pins? Anyways, I
synchronized the LOAD. Just curious...

Thanks, Sebastian

 

[Eyck Jentzsch]

Hi,

I thought the FD3 has asynchronous RESET and SET Pins? Anyways, I
synchronized the LOAD. Just curious...

Thanks, Sebastian

But no load pins...
In the load part of your statement you want to set your reg to a
variable value, set and reset only initialize to 1 or 0.

-Eyck

 

[Sebastian Becker]

I thought the FD3 has asynchronous RESET and SET Pins? Anyways, I

But no load pins...
In the load part of your statement you want to set your reg to a
variable value, set and reset only initialize to 1 or 0.

i thought synopsys is able to calculate some sort of logic functions around
the set and reset pins,something like:
(highactive Set and Reset)

RESET <= (NOT Datain) AND LoadEnable
SET <=Datain AND LoadEnable

Greets,
Sebastian

 

[Marcus Harnisch]

i thought synopsys is able to calculate some sort of logic functions around
the set and reset pins,something like:
(highactive Set and Reset)

RESET <= (NOT Datain) AND LoadEnable
SET <=Datain AND LoadEnable

But you don't want to have logic in your reset tree...

Check if there is a switch in Synopsys to force it doing what you
want.

-- Marcus

 

[Ansgar Bambynek]

Hi Sebastian,

in your original code

ELSIF load = '1' THEN
AktReg <= cin & datain(7 DOWNTO 0);

Aktreg should asynchronously get cin & datain assigned.
These values are not fixed so the synthesis tools has no knowledge of what
values should aktreg get if load is active.
Cin and all the bits of datain might be high or low when load is active so a
set or reset does not work..

HTH
Ansgar


BTW you can contact me per email and we can continue the discussion in
german