Synopsys vhdlsim (VHDL simulator)

Discussion in 'VHDL' started by gthorpe@ee.ryerson.ca, May 12, 2005.

  1. Guest

    Hi,

    Unfortunately, there is no group I can find which can address questions
    specific to synopsys-related tools like vhdlsim, so I post my question here.

    Running some VHDL simulations using 'vhdlsim', I notice that the memory
    requirements steadily increase to very large amounts with no end in sight
    (however, another simulation of the same test bench but with different
    parameters [such as the name of a data file, component speeds and clock speed]
    does not seem to get very big [approaching 1GB]). Are there any general tips on
    VHDL on how to reduce memory usage during simulation? Could this behaviour be
    due to a simulator-specific feature/bug?
    , May 12, 2005
    #1
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  2. wrote:


    > Running some VHDL simulations using 'vhdlsim', I notice that the memory
    > requirements steadily increase to very large amounts with no end in sight

    ....
    > Are there any general tips on
    > VHDL on how to reduce memory usage during simulation?


    One option may be to use unresolved data types such as
    std_ulogic(_vector) instead of std_logic(_vector) as long as possible.
    This has the advantage, that unwanted multiple drivers to one signal are
    detected and it saves the resolution function.

    But I don't have an idea how big are the differences...


    Ralf
    Ralf Hildebrandt, May 12, 2005
    #2
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  3. Mike Treseler, May 12, 2005
    #3
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