Synplify Clock Rate Question

Discussion in 'VHDL' started by Andrew Hall, Apr 12, 2004.

  1. Andrew Hall

    Andrew Hall Guest


    For my cryptography course I had to construct an AES core in VHDL. I
    duely constructed one and have verified that it works and synthesises

    Later it transpired that one of my classmates had built one with
    significantly better throughput; never one to turn down a challenge I
    pared down my implementation and made a composite entity with three
    cores, a phase-shifted clock divider and a multiplexer on the output.

    When I synthesize this (Synplify Pro 7.5.1) and look at the performance
    summary I get:

    Performance Summary

    Worst slack in design: 955.357

    Requested Estimated Requested
    Estimated Clock Clock
    Starting Clock Frequency Frequency Period
    Period Slack Type Group
    AES|clk 1.0 MHz 22.4 MHz 1000.000
    44.643 955.357 inferred Inferred_clkgroup_3
    AES|clks_inferred_clock[1] 1.0 MHz 71.6 MHz 1000.000
    13.965 986.035 inferred Inferred_clkgroup_0
    AES|clks_inferred_clock[2] 1.0 MHz 74.2 MHz 1000.000
    13.481 986.519 inferred Inferred_clkgroup_2
    AES|clks_inferred_clock[3] 1.0 MHz 71.7 MHz 1000.000
    13.945 986.055 inferred Inferred_clkgroup_1

    I'm slightly confused as to the meaning of this, on its own my AES core
    will clock at about 60Mhz. The clock divider puts out three phase
    shifted clocks with a 1:2 duty cycle so I can sort of understand the
    inferred clocks being able to go a bit faster (longer time to setup

    However, does this really mean that my main clock will only work at
    22.4Mhz?? Why so slow? This means that the individual clocks will run at
    6Mhz. It's only a simple 3 register clock divider that on its own
    synthesises to an expected performance of 150Mhz. All the main clock
    does is drive the clock divider and the output multiplexer.

    Am I reading this wrong? Is it something to do with clock buffering?
    Anybody got any suggestions for how to get my multicore system to run at
    a more sensible clock rate? (I'll add at this point that it is 66 layer
    pipelined, I have thinned out all the logic I can find, the limiting
    factor on the clock speed for the main core is a big feedback loop which
    is unavoidable).

    Thanks in advance guys,

    Andrew Hall, Apr 12, 2004
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