Synplify RAMB16 timing

[Micha Nelissen]

Hi,

Using Synplify Pro 8.2.0, targetting Xilinx Virtex-4 LX15, grade -10. I
have instantiated a RAMB16 component, but I notice that it does not matter
whether or not I set DOAREG and REGCEA to '1' or '0' (which should enable
output register), the delay from CLK to DOA is always 2.10 ns, which seems
to indicate synplify is using the delay without output register.

Does anyone know how to fix this, or what I am doing wrong ?

Thanks in advance,

Micha