Synplify RAMB16 timing

Discussion in 'VHDL' started by Micha Nelissen, Oct 5, 2005.

  1. Hi,

    Using Synplify Pro 8.2.0, targetting Xilinx Virtex-4 LX15, grade -10. I
    have instantiated a RAMB16 component, but I notice that it does not matter
    whether or not I set DOAREG and REGCEA to '1' or '0' (which should enable
    output register), the delay from CLK to DOA is always 2.10 ns, which seems
    to indicate synplify is using the delay without output register.

    Does anyone know how to fix this, or what I am doing wrong ?

    Thanks in advance,

    Micha
     
    Micha Nelissen, Oct 5, 2005
    #1
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