Syntax check not catching error

Discussion in 'VHDL' started by marc rei, Oct 17, 2006.

  1. marc rei

    marc rei Guest

    In some legacy code I found:
    if (signal <= '1') then...
    But the Xilinx ISE syntax check did NOT catch this.
    Why? Is there a way to set it up to do so?
     
    marc rei, Oct 17, 2006
    #1
    1. Advertising

  2. marc rei

    KJ Guest

    marc rei wrote:
    > In some legacy code I found:
    > if (signal <= '1') then...
    > But the Xilinx ISE syntax check did NOT catch this.
    > Why?

    It didn't "catch it" because it is not an error. It may not be what
    you want, but it is valid syntax. The "<=" in an 'if' statement means
    "less than or equal to" not "signal assignment" if that's what you're
    thinking.

    > Is there a way to set it up to do so?

    I hope not....

    KJ
     
    KJ, Oct 17, 2006
    #2
    1. Advertising

  3. marc rei wrote:

    > In some legacy code I found:
    > if (signal <= '1') then...
    > But the Xilinx ISE syntax check did NOT catch this.
    > Why? Is there a way to set it up to do so?


    Because it's not a syntax error. Signal probably is of type
    std_(u)logic (or even bit). That's an enumeration type. It is legal
    to use relational operators such as <= (less than or equal) on
    enumeration types.

    std_ulogic is defined as ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')

    So for values 'U', 'X', '0' and '1' your equation yields true, for
    'Z', 'W', 'L', 'H' and '-' it will be false.

    I wonder how it will be synthesized. I guess as "always true". In that
    case, a warning would have been nice.

    --
    Paul.
    www.aimcom.nl
     
    Paul Uiterlinden, Oct 17, 2006
    #3
  4. marc rei

    marc rei Guest

    Unfortunately it is defined as std_logic and is found several times in
    the project.

    Paul Uiterlinden wrote:
    > marc rei wrote:
    >
    > > In some legacy code I found:
    > > if (signal <= '1') then...
    > > But the Xilinx ISE syntax check did NOT catch this.
    > > Why? Is there a way to set it up to do so?

    >
    > Because it's not a syntax error. Signal probably is of type
    > std_(u)logic (or even bit). That's an enumeration type. It is legal
    > to use relational operators such as <= (less than or equal) on
    > enumeration types.
    >
    > std_ulogic is defined as ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')
    >
    > So for values 'U', 'X', '0' and '1' your equation yields true, for
    > 'Z', 'W', 'L', 'H' and '-' it will be false.
    >
    > I wonder how it will be synthesized. I guess as "always true". In that
    > case, a warning would have been nice.
    >
    > --
    > Paul.
    > www.aimcom.nl
     
    marc rei, Oct 19, 2006
    #4
  5. marc rei

    KJ Guest

    marc rei wrote:
    > Unfortunately it is defined as std_logic and is found several times in
    > the project.
    >

    Is there some question here? Your original post said that this is from
    legacy code so I presume it must be 'working' legacy code (i.e.
    performs the proper function). As explained previously, the syntax of
    the statement is not an error so what is your question?

    KJ
     
    KJ, Oct 19, 2006
    #5
  6. marc rei

    Jim Lewis Guest

    marc rei wrote:
    > In some legacy code I found:
    > if (signal <= '1') then...
    > But the Xilinx ISE syntax check did NOT catch this.
    > Why? Is there a way to set it up to do so?
    >


    "<=" is overloadable. Reference the attached package.
    There are two possible outcomes.
    1: Compile time error: Older simulators do not allow explicit
    implementations of subprograms to overload implicit ones (newer ones do).

    2: Run time warning due to code in package.

    Option 2: Make a copy of the attached package under a different
    name and reference both packages in the design - the result
    is a compile time error flagging the operator.

    Have fun,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    --
    -- File Name: munge_le_pkg.vhd
    -- Block Name: munge_le_pkg
    --
    -- Author: Jim Lewis, SynthWorks Design Inc, 503-590-4787
    --
    -- Creation Date: 10/2006
    --
    -- Description:
    -- Testbench munge_le_pkg
    --
    -- Project:
    -- SynthWorks Design Inc.
    -- Training Courses
    -- 11898 SW 128th Ave.
    -- Tigard, Or 97223
    -- http://www.SynthWorks.com
    -- email:
    --
    -- Copyright (c) 2006 by SynthWorks Design Inc. All rights reserved.
    --
    -- $Id: $
    --
    -- $Revision: $
    --
    -- Revision History:
    -- $Log: $
    --
    -- Known Bugs:
    -- None
    --
    library ieee;
    use ieee.std_logic_1164.all;

    package munge_le_pkg is

    function "<=" (L, R: std_ulogic) return boolean ;

    end munge_le_pkg ;

    package body munge_le_pkg is

    type bool_table is array(std_ulogic, std_ulogic) of boolean ;
    constant F : boolean := false ;
    constant T : boolean := true ;

    CONSTANT le_table : bool_table := (
    -- -------------------------------------------------
    -- | U X 0 1 Z W L H - | |
    -- -------------------------------------------------
    ( F, F, F, F, F, F, F, F, F ), -- | U |
    ( F, F, F, F, F, F, F, F, F ), -- | X |
    ( F, F, T, T, F, F, T, T, F ), -- | 0 |
    ( F, F, F, T, F, F, F, T, F ), -- | 1 |
    ( F, F, F, F, F, F, F, F, F ), -- | Z |
    ( F, F, F, F, F, F, F, F, F ), -- | W |
    ( F, F, T, T, F, F, T, T, F ), -- | L |
    ( F, F, F, T, F, F, F, T, F ), -- | H |
    ( F, F, F, T, F, F, F, T, F ) -- | - |
    );


    function "<=" (L, R: std_ulogic) return boolean is
    begin
    report "Suspect usage of <= with std_ulogic" severity warning ;
    return le_table(L, R) ;
    end "<=" ;

    end munge_le_pkg ;
     
    Jim Lewis, Oct 20, 2006
    #6
  7. marc rei

    KJ Guest

    "Jim Lewis" <> wrote in message
    news:...
    > marc rei wrote:
    >> In some legacy code I found:
    >> if (signal <= '1') then...
    >> But the Xilinx ISE syntax check did NOT catch this.
    >> Why? Is there a way to set it up to do so?
    >>

    >
    > "<=" is overloadable. Reference the attached package.
    > There are two possible outcomes.
    > 1: Compile time error: Older simulators do not allow explicit
    > implementations of subprograms to overload implicit ones (newer ones
    > do).
    >
    > 2: Run time warning due to code in package.
    >
    > Option 2: Make a copy of the attached package under a different
    > name and reference both packages in the design - the result
    > is a compile time error flagging the operator.
    >


    Well Jim, that's just plain cheating. The original post was complaining
    about a non-existent syntax error and now you're giving instructions for how
    to insert errors into the code in order to smoke out the error that didn't
    exist ;)

    KJ
     
    KJ, Oct 20, 2006
    #7
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Hari Sekhon

    catching syntax errors via excepthook?

    Hari Sekhon, Jul 3, 2006, in forum: Python
    Replies:
    1
    Views:
    417
    Alex Martelli
    Jul 3, 2006
  2. yawnmoth
    Replies:
    97
    Views:
    4,757
    Bent C Dalager
    Feb 27, 2009
  3. Good Night Moon
    Replies:
    9
    Views:
    291
    Rick DeNatale
    Jul 25, 2007
  4. sonet
    Replies:
    6
    Views:
    190
    J├╝rgen Exner
    Jun 17, 2007
  5. Mark Richards
    Replies:
    3
    Views:
    324
    Tad McClellan
    Nov 18, 2007
Loading...

Share This Page