Syntax check not catching error

[marc rei]

In some legacy code I found:
if (signal <= '1') then...
But the Xilinx ISE syntax check did NOT catch this.
Why? Is there a way to set it up to do so?

 

[KJ]

In some legacy code I found:
if (signal <= '1') then...
But the Xilinx ISE syntax check did NOT catch this.
Why?

It didn't "catch it" because it is not an error. It may not be what
you want, but it is valid syntax. The "<=" in an 'if' statement means
"less than or equal to" not "signal assignment" if that's what you're
thinking.

Is there a way to set it up to do so?

I hope not....

KJ

 

[Paul Uiterlinden]

In some legacy code I found:
if (signal <= '1') then...
But the Xilinx ISE syntax check did NOT catch this.
Why? Is there a way to set it up to do so?

Because it's not a syntax error. Signal probably is of type
std_(u)logic (or even bit). That's an enumeration type. It is legal
to use relational operators such as <= (less than or equal) on
enumeration types.

std_ulogic is defined as ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')

So for values 'U', 'X', '0' and '1' your equation yields true, for
'Z', 'W', 'L', 'H' and '-' it will be false.

I wonder how it will be synthesized. I guess as "always true". In that
case, a warning would have been nice.

 

[marc rei]

Unfortunately it is defined as std_logic and is found several times in
the project.

 

[KJ]

Unfortunately it is defined as std_logic and is found several times in
the project.

Is there some question here? Your original post said that this is from
legacy code so I presume it must be 'working' legacy code (i.e.
performs the proper function). As explained previously, the syntax of
the statement is not an error so what is your question?

KJ

 

[Jim Lewis]

In some legacy code I found:
if (signal <= '1') then...
But the Xilinx ISE syntax check did NOT catch this.
Why? Is there a way to set it up to do so?

"<=" is overloadable. Reference the attached package.
There are two possible outcomes.
1: Compile time error: Older simulators do not allow explicit
implementations of subprograms to overload implicit ones (newer ones do).

2: Run time warning due to code in package.

Option 2: Make a copy of the attached package under a different
name and reference both packages in the design - the result
is a compile time error flagging the operator.

Have fun,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

--
-- File Name: munge_le_pkg.vhd
-- Block Name: munge_le_pkg
--
-- Author: Jim Lewis, SynthWorks Design Inc, 503-590-4787
--
-- Creation Date: 10/2006
--
-- Description:
-- Testbench munge_le_pkg
--
-- Project:
-- SynthWorks Design Inc.
-- Training Courses
-- 11898 SW 128th Ave.
-- Tigard, Or 97223
-- http://www.SynthWorks.com
-- email: (e-mail address removed)
--
-- Copyright (c) 2006 by SynthWorks Design Inc. All rights reserved.
--
-- $Id: $
--
-- $Revision: $
--
-- Revision History:
-- $Log: $
--
-- Known Bugs:
-- None
--
library ieee;
use ieee.std_logic_1164.all;

package munge_le_pkg is

function "<=" (L, R: std_ulogic) return boolean ;

end munge_le_pkg ;

package body munge_le_pkg is

type bool_table is array(std_ulogic, std_ulogic) of boolean ;
constant F : boolean := false ;
constant T : boolean := true ;

CONSTANT le_table : bool_table := (
-- -------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- -------------------------------------------------
( F, F, F, F, F, F, F, F, F ), -- | U |
( F, F, F, F, F, F, F, F, F ), -- | X |
( F, F, T, T, F, F, T, T, F ), -- | 0 |
( F, F, F, T, F, F, F, T, F ), -- | 1 |
( F, F, F, F, F, F, F, F, F ), -- | Z |
( F, F, F, F, F, F, F, F, F ), -- | W |
( F, F, T, T, F, F, T, T, F ), -- | L |
( F, F, F, T, F, F, F, T, F ), -- | H |
( F, F, F, T, F, F, F, T, F ) -- | - |
);


function "<=" (L, R: std_ulogic) return boolean is
begin
report "Suspect usage of <= with std_ulogic" severity warning ;
return le_table(L, R) ;
end "<=" ;

end munge_le_pkg ;

 

[KJ]

"<=" is overloadable. Reference the attached package.
There are two possible outcomes.
1: Compile time error: Older simulators do not allow explicit
implementations of subprograms to overload implicit ones (newer ones
do).

2: Run time warning due to code in package.

Option 2: Make a copy of the attached package under a different
name and reference both packages in the design - the result
is a compile time error flagging the operator.

Well Jim, that's just plain cheating. The original post was complaining
about a non-existent syntax error and now you're giving instructions for how
to insert errors into the code in order to smoke out the error that didn't
exist

KJ