Syntax help

Discussion in 'VHDL' started by atul.ee@gmail.com, Nov 15, 2006.

  1. Guest

    What is the VHDL syntax to specify rise and fall time of the signal
    , Nov 15, 2006
    #1
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  2. On 15 Nov 2006 05:08:35 -0800, wrote:

    >What is the VHDL syntax to specify rise and fall time of the signal


    There is none. Logic signals in VHDL have discrete values and
    change instantaneously from one value to another. (Things are
    a little more difficult for signals of type REAL, but let's skip
    that issue for now.)

    You can mimic some of the features of risetime by making
    a signal go to 'X' for some time...

    process
    constant t_rise: time := 1 ns;
    constant t_fall: time := 2 ns;
    begin
    sig <= '0';
    wait for 10 ns;
    sig <= 'X', '1' after t_rise;
    wait for 10 ns;
    sig <= 'X', '0' after t_fall;
    ...

    But please NEVER do that with a clock signal!
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Nov 15, 2006
    #2
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  3. Guest

    Jonathan Bromley wrote:
    > On 15 Nov 2006 05:08:35 -0800, wrote:
    >
    > >What is the VHDL syntax to specify rise and fall time of the signal

    >
    > There is none. Logic signals in VHDL have discrete values and
    > change instantaneously from one value to another. (Things are
    > a little more difficult for signals of type REAL, but let's skip
    > that issue for now.)
    >
    > You can mimic some of the features of risetime by making
    > a signal go to 'X' for some time...
    >
    > process
    > constant t_rise: time := 1 ns;
    > constant t_fall: time := 2 ns;
    > begin
    > sig <= '0';
    > wait for 10 ns;
    > sig <= 'X', '1' after t_rise;
    > wait for 10 ns;
    > sig <= 'X', '0' after t_fall;
    > ...
    >
    > But please NEVER do that with a clock signal!
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    >
    > http://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    Thanks, That was helpfull.
    Atul
    , Nov 16, 2006
    #3
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