lomtik said:
Hi, how do I implement something like that in one line, so that I
don't drive DOUT at two locations?
DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='0');
Continuing with your methodology, you could write:
DOUT1 <= DO_higher(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='1')
else (others => '0') ;
DOUT2 <= DO_lower(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='0')
else (others => '0') ;
DOUT <= DOUT1 or DOUT2 ;
Otherwise, in general "when/if" for independent datapaths leads
to priority select logic (which can be slower and smaller). Note
though that priority select logic with up to 3 inputs, is
usually ok.
In VHDL-200X we are overloading "AND" to give you a simple solution
to this problem:
DOUT <=
(DO_higher(SAMPLE_WIDTH-1 downto 0) and (not CSN and not RDN and Addr(8)) or
( DO_lower(SAMPLE_WIDTH-1 downto 0) and (not CSN and not RDN and not Addr(8)) ;
-- of course if you like this, you could borrow the function from the
-- proposed ieee package and temporarily put it in yours.
For now, most of the time I prefer using case to solve this issue
as shown below. I particularly like getting the 'X' when Addr = 'X'
process(CSN, RDN, Addr, DO_higher, DO_lower)
begin
if (not CSN and not RDN) = '1' then
case Addr is
when '0' => DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) ;
when '1' => DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) ;
when others => DOUT <= (others => 'X') ; -- All X's
end case ;
else
DOUT <= (others => '0') ; -- All 0's
end if ;
end process ;
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:
[email protected]
SynthWorks Design Inc.
http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~