Syntheis report??

Discussion in 'VHDL' started by Julia_10, Aug 3, 2009.

  1. Julia_10

    Julia_10

    Joined:
    Aug 3, 2009
    Messages:
    1
    I got this in my xillinx synthesis report.. The frequency is ok. But the slack is negative,, Is this ok to continue with my design or must i edit it to achieve positive slack.. Help I so don't know..

    Thanx in advance :)

    Timing Summary:
    ---------------
    Speed Grade: -3

    Minimum period: 3.720ns (Maximum Frequency: 268.824MHz)
    Minimum input arrival time before clock: 2.543ns
    Maximum output required time after clock: 0.346ns
    Maximum combinational path delay: 2.174ns
    Julia_10, Aug 3, 2009
    #1
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