synthesis error with DC

Discussion in 'VHDL' started by rajan, Aug 30, 2004.

  1. rajan

    rajan Guest

    Hi,

    I am trying to synthesize a design with synopsys. But, keep on getting this
    error. Would anyone please make this erro message clear to me.



    Warning: Design 'design_core' has '1' unresolved references. For more
    detailed information, use the "link" command. (UID-341)
    Information: Updating design information... (UID-85)
    Allocating blocks in 'design_core'

    Error: The selector S_18 is shorted to the selector S_2.
    Resource sharing does not support operations that are
    shorted together. (SR-8)
    Error: Cannot load design 'design_core'. (DDB-76)
    0
     
    rajan, Aug 30, 2004
    #1
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  2. "rajan" wrote:
    >
    > Warning: Design 'design_core' has '1' unresolved references.


    Consider simulation before synthesis
    to correct logical errors.

    -- Mike Treseler
     
    Mike Treseler, Aug 31, 2004
    #2
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  3. On 31 Aug 2004 11:07:14 -0700, (Mike
    Treseler) wrote:

    >"rajan" wrote:
    >>
    >> Warning: Design 'design_core' has '1' unresolved references.

    >
    > Consider simulation before synthesis
    > to correct logical errors.


    It's possible there weren't any. If this was a Verilog
    design in which a variable (reg) was written at different
    times from two different "always" blocks, it could give
    correct results in simulation but yet be unsynthesisable.
    Similarly, most synthesis tools use different library
    structures than simulation tools, so it's possible to miss
    out a file from the synthesis run and get "unresolved
    reference" errors even after a successful simulation.

    Whilst I completely agree with your necessarily oft-repeated
    exhortation, it doesn't deal with all the likely problems.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Sep 1, 2004
    #3
  4. hi,
    seems like a net has more than one driver. You can see schematic in
    GTECH level(Design Analyzer),
    and try to find the s_18 and s_2 blocks and may be you find which net
    you are
    trying to drive double.

    Metin

    "rajan" <> wrote in message news:<cgvkbn$468$>...
    > Hi,
    >
    > I am trying to synthesize a design with synopsys. But, keep on getting this
    > error. Would anyone please make this erro message clear to me.
    >
    >
    >
    > Warning: Design 'design_core' has '1' unresolved references. For more
    > detailed information, use the "link" command. (UID-341)
    > Information: Updating design information... (UID-85)
    > Allocating blocks in 'design_core'
    >
    > Error: The selector S_18 is shorted to the selector S_2.
    > Resource sharing does not support operations that are
    > shorted together. (SR-8)
    > Error: Cannot load design 'design_core'. (DDB-76)
    > 0
     
    Metin Yerlikaya, Sep 1, 2004
    #4
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