synthesis of exit in for loop

Discussion in 'VHDL' started by ikbangesh, Jun 6, 2010.

  1. ikbangesh

    ikbangesh

    Joined:
    May 26, 2010
    Messages:
    2
    Hi friends
    I am new to FPGA world. I have one question, can exit command in for loop be synthesized ? if exit is true how many logic copies of for loop will be created.


    for i in 0 to 6 loop
    if i =4 then
    exit;
    end if;
    end loop;

    Many thanks
     
    ikbangesh, Jun 6, 2010
    #1
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  2. ikbangesh

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Exit From Loop

    The loop you have presented will not synthesize any hardware. If this is part of some process that you want to synthesize you need to post the entire code before someone can help you.
     
    eliascm, Jun 7, 2010
    #2
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