Hi friends
I am new to FPGA world. I have one question, can exit command in for loop be synthesized ? if exit is true how many logic copies of for loop will be created.
for i in 0 to 6 loop
if i =4 then
exit;
end if;
end loop;
Many thanks
I am new to FPGA world. I have one question, can exit command in for loop be synthesized ? if exit is true how many logic copies of for loop will be created.
for i in 0 to 6 loop
if i =4 then
exit;
end if;
end loop;
Many thanks