Synthesis of STD_LOGIC

Discussion in 'VHDL' started by Christopher Bunk, Jul 1, 2003.

  1. Hey, I got a question about synthesizing STD_LOGIC. When it's synthesized is
    it identical to a "bit". For simulation I realize that it was given other
    values such as U, -, L and H, but which of these values work for simulation?
    If I write a 'U' to it for example, and then I compare it to 'U' does that
    work in simulation. Or what values will that work for in simulation?


    Thanks.
     
    Christopher Bunk, Jul 1, 2003
    #1
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  2. Christopher Bunk wrote:
    > Hey, I got a question about synthesizing STD_LOGIC. When it's synthesized is
    > it identical to a "bit". For simulation I realize that it was given other
    > values such as U, -, L and H, but which of these values work for simulation?


    All of them.

    > If I write a 'U' to it for example, and then I compare it to 'U' does that
    > work in simulation.


    yes.

    -- Mike Treseler
     
    Mike Treseler, Jul 3, 2003
    #2
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  3. Christopher Bunk wrote:
    >
    > Oh crap. Sorry I typed that wrong. I meant what values work for synthesis.
    > I'm guessing that you can only compare to '1' and '0' for synthesis. Am I
    > right?


    Yes. There is no hardware analog of '-', 'U', 'X' or 'W' and while it
    might be possible to construct something to implement comparisons
    against 'Z', 'H', and 'L', I doubt that any synthesizer does it.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Jul 4, 2003
    #3
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