Synthesis of VHDL RTL including recursive functions

Discussion in 'VHDL' started by gpi5, Nov 9, 2004.

  1. gpi5

    gpi5 Guest

    Hi

    When a VHDL module with recursive functions is synthetised, what is
    exactly happening?
    The result is available during the same clock cycle, so I would expect the
    synthesis tool to translate the recursive nature of the algorithm into a
    'spacial' algorithm (e.g. if the recusion has a depth of 10, then there
    will be 10 'stages' on the silicon). Am I totally wrong here?

    Where can I find further details on that?
    Thanks,
    gil
     
    gpi5, Nov 9, 2004
    #1
    1. Advertising

  2. gpi5 wrote:

    > When a VHDL module with recursive functions is synthetised, what is
    > exactly happening?


    Loops of all types are an editing convenience.
    All loops are unrolled long before anything physical happens.

    > Where can I find further details on that?


    http://groups.google.com/groups?q=vhdl recursion OR recursive


    -- Mike Treseler
     
    Mike Treseler, Nov 9, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    1,206
    Technology Consultant
    Sep 9, 2003
  2. Zyd

    VHDL RTL description

    Zyd, Apr 14, 2004, in forum: VHDL
    Replies:
    1
    Views:
    1,484
    H. Li
    Apr 14, 2004
  3. Anand P Paralkar

    ASIC RTL and FPGA RTL

    Anand P Paralkar, Apr 26, 2004, in forum: VHDL
    Replies:
    1
    Views:
    4,884
    Alexander Gnusin
    Apr 26, 2004
  4. sharatd
    Replies:
    0
    Views:
    1,932
    sharatd
    Oct 18, 2006
  5. vamsi
    Replies:
    21
    Views:
    2,088
    Keith Thompson
    Mar 9, 2009
Loading...

Share This Page