Synthesis Problem

Discussion in 'VHDL' started by Joe Lancaster, Jan 7, 2005.

  1. Hi everyone!

    I've run into a problem with a design I'm working on and I hope someone
    may have had a similar problem before. I have a narrow but deep
    SelectRam with some data in it, that I am trying to read into a
    std_logic_vector. The problem is when I try to synthesize the design
    using Synplify Pro, it gives me the following error:

    "Expecting constant expression"

    which refers to this line of code:

    q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0);

    The above code is in a clocked process, and executes a finite number of
    times to load the vector. On each clock, q_up_idx and q_idx get
    incremented and q_dout is the output from the SelectRam.

    Now, the synthesizer doesn't like the dynamic index into my vector, even
    though functionally it is correct. Does anyone know of a more explicit
    way to write this so Synplify can understand what I am trying to do?

    Thanks in advance,
    Joe Lancaster
     
    Joe Lancaster, Jan 7, 2005
    #1
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  2. Joe Lancaster wrote:

    > q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0);


    Maybe your synthesis tool does not like this, because there are two
    _independent_ values for upper and lower bound: q_up_idx and q_idx. What
    happens if you just write:

    q_out_buff(q_idx+1 downto q_idx) <= q_dout(1 downto 0); --?

    Furthermore: Should q_out_buff be a latch (this is the case te the
    moment)? What value do you want for the bits, that are not assigned with
    the new value q_dout?


    Otherwise I would start with modelling every bit of q_out_buff manually:

    -- all latches!
    q_out_buff(0) = q_dout(0) when q_idx=0;
    q_out_buff(1) = q_dout(1) when q_idx=0 else
    q_dout(0) when q_idx=1; -- take care! muxed latch!
    -- and so on...

    I guess, you will find a way to describe it with a for-generate loop.


    Ralf
     
    Ralf Hildebrandt, Jan 8, 2005
    #2
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  3. Joe Lancaster wrote:
    > Hi everyone!
    >
    > I've run into a problem with a design I'm working on and I hope someone
    > may have had a similar problem before. I have a narrow but deep
    > SelectRam with some data in it, that I am trying to read into a
    > std_logic_vector. The problem is when I try to synthesize the design
    > using Synplify Pro, it gives me the following error:
    >
    > "Expecting constant expression"
    >
    > which refers to this line of code:
    >
    > q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0);
    >
    > The above code is in a clocked process, and executes a finite number of
    > times to load the vector. On each clock, q_up_idx and q_idx get
    > incremented and q_dout is the output from the SelectRam.
    >
    > Now, the synthesizer doesn't like the dynamic index into my vector, even
    > though functionally it is correct. Does anyone know of a more explicit
    > way to write this so Synplify can understand what I am trying to do?


    Try splitting the assignment up like this:

    q_out_buff(q_up_idx) <= q_dout(1);
    q_out_buff(q_idx) <= q_dout(0);

    Also, you may have to make sure that your code defines a fixed (not just
    finite) number of iterations.

    If that doesn't work, you may need to define the implied multiplexer
    explicitly and generate an explicit select signal.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Jan 9, 2005
    #3
  4. Joe Lancaster

    jtw Guest

    I had the same issue recently with Synplify; everything fine in Modelsim,
    but then ... it wouldn't synthesize. I just coded mine into a loop (I had
    more bits than the two used here), and each pass of the loop assigned each
    bit individually. (My implementation was more a barrel shifter.)

    Synthesizer is now happy.

    Jason

    "Tim Hubberstey" <> wrote in message
    news:QghEd.15004$06.872@clgrps12...
    > Joe Lancaster wrote:
    >> Hi everyone!
    >>
    >> I've run into a problem with a design I'm working on and I hope someone
    >> may have had a similar problem before. I have a narrow but deep
    >> SelectRam with some data in it, that I am trying to read into a
    >> std_logic_vector. The problem is when I try to synthesize the design
    >> using Synplify Pro, it gives me the following error:
    >>
    >> "Expecting constant expression"
    >>
    >> which refers to this line of code:
    >>
    >> q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0);
    >>
    >> The above code is in a clocked process, and executes a finite number of
    >> times to load the vector. On each clock, q_up_idx and q_idx get
    >> incremented and q_dout is the output from the SelectRam.
    >>
    >> Now, the synthesizer doesn't like the dynamic index into my vector, even
    >> though functionally it is correct. Does anyone know of a more explicit
    >> way to write this so Synplify can understand what I am trying to do?

    >
    > Try splitting the assignment up like this:
    >
    > q_out_buff(q_up_idx) <= q_dout(1);
    > q_out_buff(q_idx) <= q_dout(0);
    >
    > Also, you may have to make sure that your code defines a fixed (not just
    > finite) number of iterations.
    >
    > If that doesn't work, you may need to define the implied multiplexer
    > explicitly and generate an explicit select signal.
    > --
    > Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    > Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    > Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    >
     
    jtw, Jan 10, 2005
    #4
  5. Hello again!

    Thanks to everyone for your help.

    Good call Tim, your method worked great and I didn't have to do loops or
    enumeration! I just modified

    q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0);

    to be

    q_out_buff(q_idx + 1) <= q_dout(1);
    q_out_buff(q_idx) <= q_dout(1);

    and Synplicity is happy (and so am I). :)

    Thanks again,
    Joe

    Tim Hubberstey wrote:
    > Joe Lancaster wrote:
    >
    >> Hi everyone!
    >>
    >> I've run into a problem with a design I'm working on and I hope
    >> someone may have had a similar problem before. I have a narrow but
    >> deep SelectRam with some data in it, that I am trying to read into a
    >> std_logic_vector. The problem is when I try to synthesize the design
    >> using Synplify Pro, it gives me the following error:
    >>
    >> "Expecting constant expression"
    >>
    >> which refers to this line of code:
    >>
    >> q_out_buff(q_up_idx downto q_idx) <= q_dout(1 downto 0);
    >>
    >> The above code is in a clocked process, and executes a finite number
    >> of times to load the vector. On each clock, q_up_idx and q_idx get
    >> incremented and q_dout is the output from the SelectRam.
    >>
    >> Now, the synthesizer doesn't like the dynamic index into my vector,
    >> even though functionally it is correct. Does anyone know of a more
    >> explicit way to write this so Synplify can understand what I am trying
    >> to do?

    >
    >
    > Try splitting the assignment up like this:
    >
    > q_out_buff(q_up_idx) <= q_dout(1);
    > q_out_buff(q_idx) <= q_dout(0);
    >
    > Also, you may have to make sure that your code defines a fixed (not just
    > finite) number of iterations.
    >
    > If that doesn't work, you may need to define the implied multiplexer
    > explicitly and generate an explicit select signal.
     
    Joe Lancaster, Jan 12, 2005
    #5
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