Synthesis problem

[VHDL_lover]

I am getting errors in simulation of post synthesis VHDL file.

errors are like
----dffr is not a component declaration.
-----Statement cannot be labeled. etc for all primitives using in the
flattened file

i mapped adk library also and the condition is same.
any help will be really great.

Thanks

 

[Neo]

I think there are scan inertion cells in you netlist for which a
library has to be attached.

 

[VHDL_lover]

Thanks for reply.

what is scan inertion cells and which library need to be attached to
remove it?