Synthesis problem

Discussion in 'VHDL' started by VHDL_lover, Jan 30, 2005.

  1. VHDL_lover

    VHDL_lover Guest

    I am getting errors in simulation of post synthesis VHDL file.

    errors are like
    ----dffr is not a component declaration.
    -----Statement cannot be labeled. etc for all primitives using in the
    flattened file

    i mapped adk library also and the condition is same.
    any help will be really great.

    Thanks
    VHDL_lover, Jan 30, 2005
    #1
    1. Advertising

  2. VHDL_lover

    Neo Guest

    I think there are scan inertion cells in you netlist for which a
    library has to be attached.
    Neo, Jan 31, 2005
    #2
    1. Advertising

  3. VHDL_lover

    VHDL_lover Guest

    Thanks for reply.

    what is scan inertion cells and which library need to be attached to
    remove it?
    VHDL_lover, Feb 8, 2005
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    2,080
    Ralf Hildebrandt
    Sep 8, 2003
  2. walala
    Replies:
    4
    Views:
    1,181
    Technology Consultant
    Sep 9, 2003
  3. Andy
    Replies:
    5
    Views:
    565
  4. senthil
    Replies:
    3
    Views:
    2,438
    Ray Andraka
    Feb 5, 2004
  5. Joe Lancaster

    Synthesis Problem

    Joe Lancaster, Jan 7, 2005, in forum: VHDL
    Replies:
    4
    Views:
    1,345
    Joe Lancaster
    Jan 12, 2005
Loading...

Share This Page