Synthesis problem

Discussion in 'VHDL' started by lokesh_boddu, Oct 31, 2006.

  1. lokesh_boddu

    lokesh_boddu

    Joined:
    Oct 18, 2006
    Messages:
    6
    Hi

    i am working FPGAs,i have synthesized a design using xilinx ISE 8.1and i have a final report like below

    Device utilization summary:
    ---------------------------

    Selected Device : 2vp7fg456-5

    Number of Slices: 139 out of 4928 2%
    Number of Slice Flip Flops: 219 out of 9856 2%
    Number of 4 input LUTs: 78 out of 9856 0%
    Number of bonded IOBs: 262 out of 248 105% (*)
    Number of MULT18X18s: 7 out of 44 15%
    Number of GCLKs: 1 out of 16 6%

    WARNING:Xst:1336 - (*) More than 100% of Device resources are used

    i am not able to understand the warning,searched in the net but i am not able to fine any solution

    and when i try to implement the design in the flow i get a error
    ERROR:pack:18 - The design is too large for the given device and package.
    Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device.

    So please help me to solve this problem

    Thanks and Regards
    BODDU
    lokesh_boddu, Oct 31, 2006
    #1
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