Synthesis support for multi-dimentional arrays

Discussion in 'VHDL' started by Michael Neuling, Nov 26, 2003.

  1. I'm using XST version 6.1 and it doesn't support VHDL
    multi-dimensional arrays greater than 2. ie. this is not supported:
    type std_ulogic_3D is array (NATURAL RANGE <>,NATURAL RANGE
    <>,NATURAL RANGE <> ) of std_ulogic;

    XST gives error "Matrix not supported yet." if you instance an
    std_ulogic_3D

    What synthesis front ends are available for Xilinx FPGAs which support
    this? I've attached some VHDL code to test this...

    BTW I know I can create arrays of arrays in VHDL but this has problems
    since you need to constrain one of the dimensions. I don't want to do
    this as it will limit my design. Also, XST gets exceptions when 4 or
    more dimensions are created this way. ie. the following code breaks
    XST when you instance a std_ulogic_4D:
    type std_ulogic_2D is array ( NATURAL RANGE <> ) of
    std_ulogic_vector(1 DOWNTO 0);
    type std_ulogic_3D is array ( NATURAL RANGE <> ) of std_ulogic_2D(1
    DOWNTO 0);
    type std_ulogic_4D is array ( NATURAL RANGE <> ) of std_ulogic_3D(1
    DOWNTO 0);

    Regards,
    Michael

    -------
    library ieee;
    use ieee.std_logic_1164.all;
    package testPkg is
    type std_ulogic_3D is array ( NATURAL RANGE <>,
    NATURAL RANGE <>,
    NATURAL RANGE <> ) of std_ulogic;

    end testPkg;

    use work.testPkg.all;
    entity test is
    port (
    TestIn : in std_ulogic_3D(1 DOWNTO 0,
    1 DOWNTO 0,
    1 DOWNTO 0);

    TestOut : out std_ulogic_3D(1 DOWNTO 0,
    1 DOWNTO 0,
    1 DOWNTO 0)

    );
    end test;
    architecture rtl of test is
    begin
    TestOut <= TestIn;
    end rtl;
     
    Michael Neuling, Nov 26, 2003
    #1
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  2. Leonardo Spectrum synthesized your design => 8 wires.
    (I used an old version of LeonardoSpectrum\v2001_1b.12).

    We use Leonardo as front-end and the output is input for ISE (Xilinx) .

    Egbert Molenkamp

    "Michael Neuling" <> wrote in message
    news:...
    > I'm using XST version 6.1 and it doesn't support VHDL
    > multi-dimensional arrays greater than 2. ie. this is not supported:
    > type std_ulogic_3D is array (NATURAL RANGE <>,NATURAL RANGE
    > <>,NATURAL RANGE <> ) of std_ulogic;
    >
    > XST gives error "Matrix not supported yet." if you instance an
    > std_ulogic_3D
    >
    > What synthesis front ends are available for Xilinx FPGAs which support
    > this? I've attached some VHDL code to test this...
    >
    > BTW I know I can create arrays of arrays in VHDL but this has problems
    > since you need to constrain one of the dimensions. I don't want to do
    > this as it will limit my design. Also, XST gets exceptions when 4 or
    > more dimensions are created this way. ie. the following code breaks
    > XST when you instance a std_ulogic_4D:
    > type std_ulogic_2D is array ( NATURAL RANGE <> ) of
    > std_ulogic_vector(1 DOWNTO 0);
    > type std_ulogic_3D is array ( NATURAL RANGE <> ) of std_ulogic_2D(1
    > DOWNTO 0);
    > type std_ulogic_4D is array ( NATURAL RANGE <> ) of std_ulogic_3D(1
    > DOWNTO 0);
    >
    > Regards,
    > Michael
    >
    > -------
    > library ieee;
    > use ieee.std_logic_1164.all;
    > package testPkg is
    > type std_ulogic_3D is array ( NATURAL RANGE <>,
    > NATURAL RANGE <>,
    > NATURAL RANGE <> ) of std_ulogic;
    >
    > end testPkg;
    >
    > use work.testPkg.all;
    > entity test is
    > port (
    > TestIn : in std_ulogic_3D(1 DOWNTO 0,
    > 1 DOWNTO 0,
    > 1 DOWNTO 0);
    >
    > TestOut : out std_ulogic_3D(1 DOWNTO 0,
    > 1 DOWNTO 0,
    > 1 DOWNTO 0)
    >
    > );
    > end test;
    > architecture rtl of test is
    > begin
    > TestOut <= TestIn;
    > end rtl;
     
    Egbert Molenkamp, Nov 26, 2003
    #2
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  3. Michael Neuling

    Matt North Guest

    Michael,

    How would you create a 3D array using logic gates?
    A 2D array is simple, i.e. a memory device has 2 dimensions: the length of
    data it can store, and the addresses of each mem location.

    > BTW I know I can create arrays of arrays in VHDL but this has problems
    > since you need to constrain one of the dimensions. I don't want to do
    > this as it will limit my design.


    Again the FPGA has to physically assign hardware to your vhdl code, you have
    to constrain it so that it knows how many flip-flops/registers to give to
    that array.
    Natural Range is integer range 0 to integer'HIGH where integer'HIGH is
    2^31-1, have you tried replacing
    (natural range <>) with (0 to integer'HIGH) or the value that integer'HIGH
    takes.

    I haven't tried the above, but your synthesis tool might now see that the
    array is constrained to a finite value.
    Hope this helps.

    Matt.
     
    Matt North, Nov 26, 2003
    #3
  4. Matt,

    > How would you create a 3D array using logic gates?
    > A 2D array is simple, i.e. a memory device has 2 dimensions: the length of
    > data it can store, and the addresses of each mem location.


    If you want a 2x2x2 array (say) all it needs to create is 2 2x2
    arrays. ie. a 4x4 array.

    > Again the FPGA has to physically assign hardware to your vhdl code, you have
    > to constrain it so that it knows how many flip-flops/registers to give to
    > that array.
    > Natural Range is integer range 0 to integer'HIGH where integer'HIGH is
    > 2^31-1, have you tried replacing
    > (natural range <>) with (0 to integer'HIGH) or the value that integer'HIGH
    > takes.
    >
    > I haven't tried the above, but your synthesis tool might now see that the
    > array is constrained to a finite value.
    > Hope this helps.


    I'll try this but I don't think it'll help. The synthesis tool will
    only allocate resources after it sees an instance of the type and not
    when it sees the type definition. Otherwise just seeing the
    std_ulogic_vector type definition would send it crazy trying to
    allocate 4 billion resources.

    Actually, it doesn't even know at instance time what kind resource
    (logic, wire, FF etc.) it's allocating or even how many of those
    resources are truly required in the final optimised logic.

    Regards,
    Michael
     
    Michael Neuling, Nov 26, 2003
    #4
  5. Looking a little deeper at the VHDL RTL synthesis subset (1076.6-1999)
    in 8.3.2.1 on Array types:
    "The index constraint shall contain exactly one discrete range".

    So the synthesis tools don't even have to support 2D arrays.

    Regards,
    Michael
     
    Michael Neuling, Nov 27, 2003
    #5
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