Synthesis VS Simulation

Joined
Jul 21, 2009
Messages
2
Reaction score
0
Hi all

I recently started to learn VHDL as i needed for my project but i still do not undestand the dofference between designs for synthesis and simulation could some one please help me with this matter .
thanks for your time
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,743
Messages
2,569,478
Members
44,899
Latest member
RodneyMcAu

Latest Threads

Top