Synthesis VS Simulation

Discussion in 'VHDL' started by hayaloo, Jul 21, 2009.

  1. hayaloo

    hayaloo

    Joined:
    Jul 21, 2009
    Messages:
    2
    Hi all

    I recently started to learn VHDL as i needed for my project but i still do not undestand the dofference between designs for synthesis and simulation could some one please help me with this matter .
    thanks for your time
    hayaloo, Jul 21, 2009
    #1
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