synthesis

Discussion in 'VHDL' started by rajan, Sep 14, 2004.

  1. rajan

    rajan Guest

    Hi,

    I have another question, I want to put the constraint of 3 ns for the setup
    time. Is the following a right way to do?

    >>> set_input_delay -clock clk_ideal_one 3.0 [find -ports -input -no_clocks

    clk_in] <<<


    What does this command do during synthesis.

    Looking forward to hear from the experts.

    Thanks in advance.
    rajan, Sep 14, 2004
    #1
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