synthesizable delay using vhdl

Discussion in 'VHDL' started by ravi33811, Sep 13, 2007.

  1. ravi33811

    ravi33811

    Joined:
    Sep 6, 2007
    Messages:
    2
    --------------------------------------------------------------------------------

    hi can any tell how to writ vhdlcode
    to introduce delay which is synthesizable

    like
    a<=b after 50 ns;
    c<= d after 30 ns
    ravi33811, Sep 13, 2007
    #1
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