synthesize floating point

Discussion in 'VHDL' started by sanborne, Dec 4, 2008.

  1. sanborne

    sanborne Guest

    Sorry to be posting so frequently, but the information I have gotten
    so far has been fantastic.

    So one more question: Is it possible to synthesize floating point
    data? I have heard that it is not, but some of the things I have seen
    in my research of fixed point seems to indicate that it is possible to
    synthesize VHDL REAL data. And it really seems that if floating point
    data can never be synthesized, this is a huge gap that someone out
    there must be working on.

    Is there any documentation related to this question that someone could
    point me to?
     
    sanborne, Dec 4, 2008
    #1
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  2. sanborne wrote:

    > Is it possible to synthesize floating point
    > data?


    http://www.vhdl.org/fphdl/vhdl.html

    I have heard that it is not, but some of the things I have seen
    > in my research of fixed point seems to indicate that it is possible to
    > synthesize VHDL REAL data.


    I use real constants in synthesis
    to calculate integer constants.
     
    Mike Treseler, Dec 4, 2008
    #2
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  3. Hello,

    On 4 Dez., 23:33, sanborne <> wrote:
    > So one more question: Is it possible to synthesize floating point
    > data? I have heard that it is not, but some of the things I have seen


    It is possible. But not as easy as writting y = a*b and every tool did
    a good job for you.
    You need either a tool that mange this code (behavioral synthesis
    tool) or you need to rewrite this code in a way that the result can be
    processed by every tool (e.g. using slv and doing the math by shifting
    mantisse, multipliying it and adding exponents than normalize result).

    bye Thomas
     
    Thomas Stanka, Dec 5, 2008
    #3
  4. sanborne

    Tricky Guest

    On 4 Dec, 22:33, sanborne <> wrote:
    > Sorry to be posting so frequently, but the information I have gotten
    > so far has been fantastic.
    >
    > So one more question: Is it possible to synthesize floating point
    > data? I have heard that it is not, but some of the things I have seen
    > in my research of fixed point seems to indicate that it is possible to
    > synthesize VHDL REAL data. And it really seems that if floating point
    > data can never be synthesized, this is a huge gap that someone out
    > there must be working on.
    >
    > Is there any documentation related to this question that someone could
    > point me to?


    It is, but probably not in the way you are expecting.

    The VHDL Real type is NOT synthesisable. It can only be used for
    testbenching or setup constants/generics only.

    But floating point IS possible. an IEEE FP number is just a 32 bit
    number, but the arithmatic is fairly complicated compared to fixed
    point. Both Xilinx and Altera have libraries of FP components that
    will pipeline floating point arithmatic (latencies of 3-4 clock cycles
    is fairly standard, but they can be parameterised), but they are
    expensive in terms of logic compared to fixed point.

    Personally, I would exhaust all avenues of fixed point before moving
    to floating point. The IEEE float_pkg is a great addition to the
    standard, but it will not produce a useful pipelined architectures at
    the moment. The implementations of the float package for the different
    vendors appear to recommend shortened FP numbes (like a 15bit mantissa
    instead of 23).

    If you have Quartus then info on the Altera FP components can be found
    via Help->Megafunctions/LPM->Arithemtic megafunctions. All floating
    point blocks are named altfp_...

    The only downside to using the vendor libraries is that they are
    vendor dependent, on purpose.
     
    Tricky, Dec 5, 2008
    #4
  5. sanborne

    Tricky Guest

    Actually, the latencies vary alot.

    In Altera, the default for a fp adder is 11 clocks, and a divider is
    41 clocks.
     
    Tricky, Dec 5, 2008
    #5
  6. sanborne

    ajjc Guest

    On Dec 4, 2:33 pm, sanborne <> wrote:
    > Sorry to be posting so frequently, but the information I have gotten
    > so far has been fantastic.
    >
    > So one more question: Is it possible to synthesize floating point
    > data? I have heard that it is not, but some of the things I have seen
    > in my research of fixed point seems to indicate that it is possible to
    > synthesize VHDL REAL data. And it really seems that if floating point
    > data can never be synthesized, this is a huge gap that someone out
    > there must be working on.
    >
    > Is there any documentation related to this question that someone could
    > point me to?


    You can also use the FPGA coprocessor floating point package:

    http://libhdlfltp.sourceforge.net

    In the next release(soon), Altera qualification is added,
    as are pipelined sin,cos, some bug fixes, and a working board example.

    alan
     
    ajjc, Dec 5, 2008
    #6
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