Synthesizeable shared variable?

[gthorpe]

Hi,

Is it generally possible to synthesize shared variables if you write the code
such that one process is responsible for writing the variable and another
process only reads the variable?

E.g. I have the following example code (not my real design, but shows the
general idea):

library ieee;
use ieee.std_logic_1164.all;

entity sharedtest is
port(
clk, reset : in std_ulogic;
activate : out std_ulogic_vector(3 downto 0)
);
end entity sharedtest;

architecture only of sharedtest is
shared variable sel : std_ulogic_vector(activate'range);

signal int_activate : std_ulogic_vector(3 downto 0);
begin
activate <= int_activate;

process(clk, reset)
begin
if(reset = '1') then
int_activate <= (others=>'0');
elsif(rising_edge(clk)) then
int_activate <= sel;
end if;
end process;

process(int_activate)
begin
if(int_activate = X"0") then
sel := X"1";
else
sel(3) := '0';
sel(2 downto 0) := int_activate(3 downto 1);
end if;
end process;
end architecture only;

This code seems to be sythesizeable under Synopsys (it analyzes, elaborates and
compiles without errors/warnings), but will this be true for other synthesis
tools? Would this style (only one process writes, multiple may read) lead in
general to designs which are synthesizable but use shared variables?

 

[Mike Treseler]

Is it generally possible to synthesize shared variables if you write the code
such that one process is responsible for writing the variable and another
process only reads the variable?

Seems that you have positive results
for Quartus 5.1, if this is what you expected:
http://home.comcast.net/~mike_treseler/sharedtest.pdf

-- Mike Treseler