Synthesizing high-density designs in Quartus

[Divyang M]

Hi,

My design takes an input image and creates three scaled images, and
passes these through a set of 2-D FIR filter to get phase information
of the image. There are a total of 18 different outputs for the
design.

I give the whole design to Quartus to synthesize and Place & Route. The
results are correct when I only am using 1 output
at a time. It synthesizes away all the logic that is not used (the
remaining design is about 5% of the chip).
But, when I use all the 18 outputs, the results change (depending on
which machine I run Quartus on..the results are sometimes total garbage
and on other still legible but not correct). The design is now larger
(but still only 20% of the Altera Stratix S80 chip that I am using).

My guess here is that my VHDL code is correct but Quartus is having a
problem doing the routing. I've simulated and it works fine too. Is my
thinking correct?

Any advice on how I can go about doing the synthesis (any paramentes to
set in Quartus) so that it gives correct results?

One thing I've been looking at is doing incremental synthesis..so I
will compile one module, then the next, and so on..hoping this will
give the correct results (as it is supposed to NOT change the
previously synthesized modules)? Any advice on that or other
techniques?

I would greatly appreciate your help in this.

Thanks,
Divyang M.

 

[Ben Twijnstra]

Hi Divyang,

I give the whole design to Quartus to synthesize and Place & Route. The
results are correct when I only am using 1 output
at a time. It synthesizes away all the logic that is not used (the
remaining design is about 5% of the chip).
But, when I use all the 18 outputs, the results change (depending on
which machine I run Quartus on..the results are sometimes total garbage
and on other still legible but not correct). The design is now larger
(but still only 20% of the Altera Stratix S80 chip that I am using).

Not much we can help you with without code or message logs.

You may be running into a bug in the Quartus synthesizer. P&R just takes the
flattened netlist and doesn't do much with it (unless you've got all the
retiming/resynthesis stuff enabled).

On the other hand, you may have written some construct that is not fully
understood by Quartus. I suggest that you carefully examine the synthesis
message log first.

Best regards,



Ben

 

[Divyang M]

Hi Ben,

I will look at the synthesis log again and see if I find something
going on there. So far, I only see that so-and-so registers are stuck
to GND (which is fine I hope becasue at this point I have some MSBs as
'0' for multiplication/add by a constant)

What worries me is that most of my design is made up of a few blocks
(such as 2-D FIR filters) so if one set of them work, why not all of
them when used together? They're all coded the same way.

Also, I have no timing set-up (tsu) and timing-hold (th) constraints
(except one for each which come from another part of the design to
communicate with the board over a PCI bus by someone esle). Could
someone guide me as to where I can learn more about TSU and TH and how
to deteremine these for my design. The only constraint I give Quartus
is Fmax which it meets. Should that be enough or do I have to determin
TSU and TH?

Thanks,

Divyang M

 

[Ben Twijnstra]

Hi Divyang M,

What worries me is that most of my design is made up of a few blocks
(such as 2-D FIR filters) so if one set of them work, why not all of
them when used together? They're all coded the same way.

Well, all by themselves they might work fine, but if you multiplex or
cascade the outputs wrong, Quartus may find that your design's output is
not dependant on, say, filters 7 and 12.

Also, I have no timing set-up (tsu) and timing-hold (th) constraints
(except one for each which come from another part of the design to
communicate with the board over a PCI bus by someone esle). Could
someone guide me as to where I can learn more about TSU and TH and how
to deteremine these for my design. The only constraint I give Quartus
is Fmax which it meets. Should that be enough or do I have to determin
TSU and TH?

I tend to find Tco constraints quite useful. I normally use Tsu constraints
set to half a clock period to make sure that the input data gets clocked in
properly. This avoids the problem that certain registers clock in data
sample (n), while others clock in sample (n+1) if the Tsu is larger than 1
period (this can happen with, e.g. big muxes and other combinatorial stuff
before the first line of registers.

Instead of a global Fmax constraint I do tend to create clock domains and
assign them to their respective signals, mostly to remove yet another
Quartus warning. However, if you're working with a multi-clock design you
_really_ should use this technique since at that point Quartus will take
the individual frequencies and phases into account during P&R.

I personally never ran into a situation where I needed a Th constraint, but
it may be an idea to set this to 0, in order to avoid negative hold timing.
A colleague of mine once ran into this, although we never figured out why
(we didn't take more than ten minutes to think about it either, btw ;-) ).

Hope this helps a bit.

Good luck!



Ben

 

[Divyang M]

Hi Ben,

Thank you for your suggestions.

Some of them I understand..others I need more time to reflect on and
figure out how to implement them in my design. I will do that over the
next few days and see how it goes.

Divyang M