synthesizing many modules

Discussion in 'VHDL' started by cosmonutt, Jul 23, 2008.

  1. cosmonutt

    cosmonutt

    Joined:
    Jul 23, 2008
    Messages:
    1
    hi all
    i was wondering if someone here could help me with a synthesis question.
    i would like to know how to bring together a no. of separately synthesized modules at the top level.
    i have synthesized the various parts of an execution unit separately like alu , divisor etc now i want to join them using the top level file. how should i go about it. ?? should i read the netlists along with the top level file (i'm really stuck)

    thanks!
     
    cosmonutt, Jul 23, 2008
    #1
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