.....Synthesizing signals

Discussion in 'VHDL' started by knight, Dec 22, 2007.

  1. knight

    knight

    Joined:
    Dec 12, 2007
    Messages:
    4
    Hi... 2 questionz...

    Que 1...

    1) we declare a signal
    2) not initialising any value to it ( on reset or any other way)
    3) we are processing it in code

    will it take default any default value as per the compiler or
    will it always be in uninitialised state ( or in unknown state ) ???

    Example :-

    ...
    signal x;
    ...
    ...
    x <= x and p; ( x is not initialised any value and p is '1' )
    ...
    ...

    How this is synthesised...? and what will be the synthesis o/p ..?



    Que 2...

    ...
    signal x :std_logic := '1';
    ...
    how this is synthsized ....?



    thanks
    knight
    knight, Dec 22, 2007
    #1
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