System Tasks in VHDL

K

kedarpapte

Hi All,

Do we have any System Tasks and Function in VHDL similar to Verilog
like $stop, $finish

which can be easily used to halt the simulation.

Regards,
Kedar
 
D

David R Brooks

Hi All,

Do we have any System Tasks and Function in VHDL similar to Verilog
like $stop, $finish

which can be easily used to halt the simulation.
Afaik, not explicitly.
But simulation is defined to halt when no events remain to simulate. I
put a control input on my testbench's main clock oscillator, which can
be asserted when I want to halt. With no further clock events, things
stop very quickly.
 
T

Thomas Thorsen

Hi All,

Do we have any System Tasks and Function in VHDL similar to Verilog
like $stop, $finish

which can be easily used to halt the simulation.

I use:

ASSERT false REPORT "Test complete";

Which is fairly non-intrusive (but don't get confused about the apparant
"error" in the log)
 
M

Mike Treseler

Thomas said:
I use:
ASSERT false REPORT "Test complete";

Which is fairly non-intrusive (but don't get confused about the apparant
"error" in the log)

Just say :

REPORT "Test complete";

to eliminate the "error".

-- Mike Treseler
 
M

Mark McDougall

David said:
Afaik, not explicitly.
But simulation is defined to halt when no events remain to simulate. I
put a control input on my testbench's main clock oscillator, which can
be asserted when I want to halt. With no further clock events, things
stop very quickly.

I use "wait;"
 
R

Reiner Huober

Do we have any System Tasks and >Function in VHDL similar to Verilog
like $stop, $finish

Unfortunately not. The recommended way is, as other posters said, to
stop all events, i.e. stop all clocks and stimuli.

This is not always possible, expecially when the unit under test
contains vendor supplied PLL/DLL models which cannot be stopped and you
do not want to or cannot change the supplied VHDL code.

The mostly used way is to provoke an error by an ASSERT (VHDL'87) or
REPORT (VHDL'87, VHDL'93) statement with severity failure, which is
rather unpleasant.

Hubble.
 
M

Mike Treseler

Sorry, I totally missed the point.

I use a testbench done signal
to stop the clock:

if done_s then wait; end if; -- Stop clock

-- Mike Treseler
 
J

Jim Lewis

Kedar,
It will be in the Accellera VHDL-2006 revision.
Make sure to let your vendors know that you want
it implemented right away.

Cheers,
Jim
Hi All,

Do we have any System Tasks and Function in VHDL similar to Verilog
like $stop, $finish

which can be easily used to halt the simulation.

Regards,
Kedar


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

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