System Verilog & the VHDL user

Discussion in 'VHDL' started by Niv, Apr 16, 2008.

  1. Niv

    Niv Guest

    Hi all, we currently use VHDL for all our design & verification via
    testbenches.
    I have been asked to look at alternative verification methodologies,
    particularly SystemVerilog.

    (I've been on a PSL course a few years ago, but until now never had
    the tool(s) to exploit it's use, but
    people seem to think SysVerilog may be a better approach anyway.

    So, what is the best book(s) to learn SV for a VHDL conversant
    audience, and possibly more important,
    whare can we quickly learn what SV can do for us above and beyond VHDl
    testbenches.

    (Cross posted to Verilog group)

    Regards, Niv.
    Niv, Apr 16, 2008
    #1
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  2. Niv

    Dal Guest

    Approaching a similar decision myself. Have you considered SystemC?

    I would also like to know what SV can do above and beyond SC and VHDL.

    Darrin
    Dal, Apr 16, 2008
    #2
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  3. Niv

    HT-Lab Guest

    "Niv" <> wrote in message
    news:...
    > Hi all, we currently use VHDL for all our design & verification via
    > testbenches.
    > I have been asked to look at alternative verification methodologies,
    > particularly SystemVerilog.


    SystemVerilog is a language, not a verification methodology. Perhaps you
    should focus on the required methodology first and then look at the
    available languages and tools?

    >
    > (I've been on a PSL course a few years ago, but until now never had
    > the tool(s) to exploit it's use,


    Yes unfortunately the tools for PSL/SVA are quite expensive, lets hope
    VHDL2007/8 will introduce more people to the power of assertions and as such
    bring the price down.

    > but
    > people seem to think SysVerilog may be a better approach anyway.


    Better approach for what, Assertion Based Verification(ABV), Testbench
    Development, Constrained Random(CR), Transaction Level Modelling(TLM),
    fixed/floating point modelling?

    > So, what is the best book(s) to learn SV for a VHDL conversant
    > audience, and possibly more important,
    > whare can we quickly learn what SV can do for us above and beyond VHDl
    > testbenches.


    Probably less than what you would expect. As posted some time ago VHDL can
    be used for TLM, CR, ABV (using PSL) but probably not as easy as with a
    modern language like SystemVerilog/SystemC.

    Another option as suggested by Darrin is to look at SystemC. The advantage
    of SystemC is that you can add it to a "lowcost" simulator like Modelsim PE
    (no need to go to SE/Questa) and it will give you access to TLM, CR, OO and
    a very easy C/C++ interface to your PE VHDL.

    Hans
    www.ht-lab.com


    >
    > (Cross posted to Verilog group)
    >
    > Regards, Niv.
    HT-Lab, Apr 16, 2008
    #3
  4. Niv

    Niv Guest

    On 16 Apr, 12:47, "HT-Lab" <> wrote:
    > "Niv" <> wrote in message
    >
    > news:...
    >
    > > Hi all, we currently use VHDL for all our design & verification via
    > > testbenches.
    > > I have been asked to look at alternative verification methodologies,
    > > particularly SystemVerilog.

    >
    > SystemVerilog is a language, not a verification methodology. Perhaps you
    > should focus on the required methodology first and then look at the
    > available languages and tools?
    >
    >
    >
    > > (I've been on a PSL course a few years ago, but until now never had
    > > the tool(s) to exploit it's use,

    >
    > Yes unfortunately the tools for PSL/SVA are quite expensive, lets hope
    > VHDL2007/8 will introduce more people to the power of assertions and as such
    > bring the price down.
    >
    > > but
    > > people seem to think SysVerilog may be a better approach anyway.

    >
    > Better approach for what, Assertion Based Verification(ABV), Testbench
    > Development, Constrained Random(CR), Transaction Level Modelling(TLM),
    > fixed/floating point modelling?
    >
    > > So, what is the best book(s) to learn SV for a VHDL conversant
    > > audience, and possibly more important,
    > > whare can we quickly learn what SV can do for us above and beyond VHDl
    > > testbenches.

    >
    > Probably less than what you would expect. As posted some time ago VHDL can
    > be used for TLM, CR, ABV (using PSL) but probably not as easy as with a
    > modern language like SystemVerilog/SystemC.
    >
    > Another option as suggested by Darrin is to look at SystemC. The advantage
    > of SystemC is that you can add it to a "lowcost" simulator like Modelsim PE
    > (no need to go to SE/Questa) and it will give you access to TLM, CR, OO and
    > a very easy C/C++ interface to your PE VHDL.
    >
    > Hanswww.ht-lab.com
    >
    >
    >
    >
    >
    > > (Cross posted to Verilog group)

    >
    > > Regards, Niv.- Hide quoted text -

    >
    > - Show quoted text -


    We do have ModelSim SE & Questa, so that's not an issue.
    However, no-one is really using Questa at the moment due to lack of
    understanding of what we can do with it.

    We currently do large FPGA designs and test using VHDL testbenches
    (quite a lot of VHDL ASSERT statements are used).
    I've been led to believe (possibly erroneously) that with
    SystemVeilog, the assertions are more comprehensive & simpler to
    apply.
    I realise that SV is a language & not a methodology; and there seems a
    general consensus here that SV will "win" over SystemC;
    although that could be rubbish.

    We want to address our verification methodology to make it more
    thorough & hopefully simpler, albeit having to learn SV on top of
    VHDL. (Why no SystemVHDL?)

    Niv.
    Niv, Apr 16, 2008
    #4
  5. Niv

    HT-Lab Guest

    "Niv" <> wrote in message
    news:...
    > On 16 Apr, 12:47, "HT-Lab" <> wrote:
    >> "Niv" <> wrote in message
    >>

    ...
    >>
    >> > Regards, Niv.- Hide quoted text -

    >>
    >> - Show quoted text -

    >
    > We do have ModelSim SE & Questa, so that's not an issue.
    > However, no-one is really using Questa at the moment due to lack of
    > understanding of what we can do with it.
    >


    In that case I would suggest studying the AVM/OVM which is quite a
    comprehensive verification environment and supported by Questa. You can
    download a free copy from the Mentor website

    http://www.mentor.com/products/fv/_3b715c/


    > We currently do large FPGA designs and test using VHDL testbenches
    > (quite a lot of VHDL ASSERT statements are used).
    > I've been led to believe (possibly erroneously) that with
    > SystemVeilog, the assertions are more comprehensive & simpler to
    > apply.


    I am not sure about more comprehensive but given that they are part of the
    language you might be right with respect to applying them. However, as you
    probably agree, adding PSL statements in comments (or link in a vunit) is
    not such a big issue. In VHDL2007/8 comments are no longer required for PSL
    and if I understand the P1076 reference manual correctly vunits can be used
    as packages.

    > I realise that SV is a language & not a methodology; and there seems a
    > general consensus here that SV will "win" over SystemC;
    > although that could be rubbish.


    I think that is indeed rubbish since we are not talking about HD-DVD versus
    Blu-Ray, SV and SC have non-overlapping capabilities. SV is closer to the
    hardware has build in assertions and is more capable in functional
    verification (functional coverage is much easier in SV than SC) to name a
    few. SystemC on the other hand is more capable in terms of high-level
    modelling (better OO support), so if you want to model a complete SoC
    including say an Operating System you would pick SystemC over SystemVerilog.

    >
    > We want to address our verification methodology to make it more
    > thorough & hopefully simpler, albeit having to learn SV on top of
    > VHDL. (Why no SystemVHDL?)


    It is always good to learn another language so your effort on SV will not be
    wasted, just make sure you don't throw out the baby with the bathwater :)

    Hans
    www.ht-lab.com


    >
    > Niv.
    HT-Lab, Apr 16, 2008
    #5
  6. > On 16 Apr, 12:47, "HT-Lab" <> wrote:
    >> SystemVerilog is a language, not a verification methodology. Perhaps you
    >> should focus on the required methodology first and then look at the
    >> available languages and tools?


    Exactly.

    Niv wrote:

    > We do have ModelSim SE & Questa, so that's not an issue.
    > However, no-one is really using Questa at the moment due to lack of
    > understanding of what we can do with it.


    You may be able to do what you need with plain vhdl.
    Make sure the testbench stim and response data is properly synchronized.
    Use STA to verify timing, not the testbench.
    Make a synchronous watcher process for global/mulicycle assertions.

    > We want to address our verification methodology to make it more
    > thorough & hopefully simpler, albeit having to learn SV on top of
    > VHDL. (Why no SystemVHDL?)


    I agree with Hans.
    Focus on what is missing in your existing testbench suites.
    You may or may not need a new language.

    -- Mike Treseler
    Mike Treseler, Apr 16, 2008
    #6
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