SystemC + VHDL cosim, hierarchy probing, etc...

Discussion in 'VHDL' started by jjohnson@cs.ucf.edu, Dec 16, 2004.

  1. Guest

    Does anyone have any experiences to share regarding SystemC and VHDL in
    a mixed-language simulation? (ModelSim is my simulator, but all
    relevant comments are welcome.)

    We don't have a SystemC license yet for ModelSim, but wonder if adding
    SystemC to our mostly-VHDL simulation/synthesis environment will buy us
    much.

    (We *eventually* want to model FPGAs and ASICs along with an external
    uP running real code, but the first goal is just to create faster, more
    powerful testbenches for single FPGAs).

    Does SystemC allow "easy" monitoring/driving of low-level signals (deep
    in the hierarchy) from a top-level testbench?

    (By "easy", I mean something like a hierarchical instance name
    references to ports and signals, like DUT/CORE/U1/DEMOD/IQout ala
    verilog), not the hoops VHDL makes you jump through. 8-P [This is
    almost reason enough for me to finally abandon VHDL...)

    If SystemC allows the hierarchical name references, can those descend
    into the VHDL hierarchy as well? (In some or all simulators?)
    Thanks very much,

    mj
     
    , Dec 16, 2004
    #1
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  2. Alan Fitch Guest

    <> wrote in message
    news:...
    >
    > Does anyone have any experiences to share regarding SystemC and VHDL

    in
    > a mixed-language simulation? (ModelSim is my simulator, but all
    > relevant comments are welcome.)
    >
    > We don't have a SystemC license yet for ModelSim, but wonder if

    adding
    > SystemC to our mostly-VHDL simulation/synthesis environment will buy

    us
    > much.
    >
    > (We *eventually* want to model FPGAs and ASICs along with an

    external
    > uP running real code, but the first goal is just to create faster,

    more
    > powerful testbenches for single FPGAs).
    >
    > Does SystemC allow "easy" monitoring/driving of low-level signals

    (deep
    > in the hierarchy) from a top-level testbench?
    >
    > (By "easy", I mean something like a hierarchical instance name
    > references to ports and signals, like DUT/CORE/U1/DEMOD/IQout ala
    > verilog), not the hoops VHDL makes you jump through. 8-P [This is
    > almost reason enough for me to finally abandon VHDL...)
    >
    > If SystemC allows the hierarchical name references, can those

    descend
    > into the VHDL hierarchy as well? (In some or all simulators?)
    > Thanks very much,
    >
    > mj
    >



    A couple of simulators support "out of module references", for
    instance
    ncsim. This allows you to directly access hierarchical names in either
    VHDL or Verilog.

    There is also an hdl connection API in the SystemC Verification
    Library,
    which Modelsim supports (as do other simulators).

    And of course in Modelsim, there is nothing to stop you using the PLI
    in C and linking that to SystemC code,

    regards
    Alan

    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

    Fax: +44 (0)1425 471573 Web:
    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Dec 17, 2004
    #2
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  3. Jim Lewis Guest

    wrote:

    > Does anyone have any experiences to share regarding SystemC and VHDL in
    > a mixed-language simulation? (ModelSim is my simulator, but all
    > relevant comments are welcome.)
    >
    > We don't have a SystemC license yet for ModelSim, but wonder if adding
    > SystemC to our mostly-VHDL simulation/synthesis environment will buy us
    > much.
    >
    > (We *eventually* want to model FPGAs and ASICs along with an external
    > uP running real code, but the first goal is just to create faster, more
    > powerful testbenches for single FPGAs).
    >
    > Does SystemC allow "easy" monitoring/driving of low-level signals (deep
    > in the hierarchy) from a top-level testbench?
    >
    > (By "easy", I mean something like a hierarchical instance name
    > references to ports and signals, like DUT/CORE/U1/DEMOD/IQout ala
    > verilog), not the hoops VHDL makes you jump through. 8-P [This is
    > almost reason enough for me to finally abandon VHDL...)

    Most simulators have a package that allows a not so hard method
    to access internal signals. In ModelSim it is called SignalSpy.
    In Cadence it is NCMirror. Both of these packages have been
    donated to IEEE and are being used as the basis for a standard
    method along these lines.

    I have found that VHDL does have enough language features to
    create a powerful transaction based testbench environment.
    It just takes a little work - just like it would take in other
    programming languages. For some hints, see the testbench papers
    on our website: http://www.synthworks.com/papers

    The big advantage to "C" at this point, is the standard
    libraries that are available. This is one point that needs
    to be further developed and standardized in VHDL - some of
    this work is in process. Note thought that the standards
    groups are looking for volunteers in this area.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Dec 20, 2004
    #3
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